POSITIVE-ON AND NEGATIVE-OFF SUBSTRATE BIASING FOR A TRANSISTOR STRUCTURE THAT USES A TWO-DIMENSIONAL ELECTRON GAS

1 . A transistor configured to have a dynamically biased substrate alternating between position and negative voltages during operation, the transistor comprising:

a barrier semiconductor layer;

a channel semiconductor layer immediately beneath the barrier semiconductor layer to form a heterojunction interface with the barrier semiconductor layer, the heterojunction inducing a two-dimensional electron gas (2DEG) within the channel semiconductor layer;

a source contact in conductive contact with the 2DEG;

a drain contact in conductive contact with the 2DEG;

a gate terminal that is proximate to the 2DEG such that voltages applied to the gate terminal control whether the 2DEG is continuous between the source contact and the drain contact;

a semiconductor substrate beneath and rigidly coupled to the channel semiconductor layer and the barrier semiconductor layer;

a substrate contact layer disposed immediately beneath the semiconductor substrate, the substrate contact layer being electrically disconnected from the source contact to allow for a different voltage to be applied to the substrate contact layer as compared to the source contact; and

a biasing circuit configured to bias the semiconductor substrate to a negative bias voltage when the transistor is off.

2 . The transistor in accordance with claim 1 , the biasing circuit also configured to bias the substrate to a positive bias voltage when the transistor is on.

3 . The transistor of claim 2 , the semiconductor substrate being a Silicon substrate.

4 . The transistor of claim 2 , the barrier semiconductor layer being an AlGaN layer, the channel semiconductor layer being a GaN layer.

5 . The transistor of claim 2 , the biasing circuit being fabricated sharing portions of the same epitaxial layer as the barrier semiconductor layer and the channel semiconductor layer.

6 . The transistor of claim 2 , the biasing circuit being configured such that the positive bias voltage has a maximum voltage of more than 40 Volts.

7 . The transistor of claim 2 , the biasing circuit being configured such that the positive bias voltage has a maximum voltage of more than 40 Volts.

8 . The transistor of claim 7 , the biasing circuit being configured such that the negative bias voltage has a minimum voltage of less than negative 40 Volts.

9 . The transistor of claim 2 , the biasing circuit being configured such that the negative bias voltage has a minimum voltage of less than negative 40 Volts.

10 . The transistor of claim 2 , the biasing circuit being configured such that the positive bias voltage has a maximum voltage of more than 100 Volts.

11 . The transistor of claim 2 , the biasing circuit being configured such that the negative bias voltage has a minimum voltage of less than negative 100 Volts.

12 . The transistor of claim 2 , the biasing circuit being connected to the semiconductor substrate contact layer with a wire that is outside of a die that contains the transistor.

13 . The transistor of claim 2 , the channel semiconductor layer and the barrier semiconductor layer formed by epitaxially deposition of an epitaxial stack on the semiconductor substrate, the channel semiconductor layer and the barrier semiconductor layer being formed of a part of the epitaxial stack, the biasing circuit being separate and distinct from the epitaxial stack, the biasing circuit being coupled with the epitaxial stack.

14 . A method for biasing a substrate of a transistor, the transistor having a barrier semiconductor layer, a channel semiconductor layer immediately beneath the barrier semiconductor layer to form a heterojunction interface with the barrier semiconductor layer, the heterojunction inducing a two-dimensional electron gas (2DEG) within the channel semiconductor layer, the transistor further having a source contact in conductive contact with the 2DEG, a drain contact in conductive contact with the 2DEG, a gate terminal that is proximate to the 2DEG such that voltages applied to the gate terminal control whether the 2DEG is continuous between the source contact and the drain contact, a semiconductor substrate beneath and rigidly coupled to the channel semiconductor layer and the barrier semiconductor layer, and a substrate contact layer disposed immediately beneath the semiconductor substrate, the substrate contact layer being electrically disconnected from the source contact to allow for a different voltage to be applied to the substrate contact layer as compared to the source contact, the method further comprising:

detecting a pre-condition for applying a negative bias voltage to the substrate contact layer, and in response applying the negative bias voltage to the substrate contact layer.

15 . The method in accordance with claim 14 , the method further comprising detecting a pre-condition for applying a positive bias voltage to the substrate contact layer, and in response applying the positive bias voltage to the substrate contact layer.

16 . The method in accordance with claim 15 , the pre-condition for applying the positive bias voltage being the detection that the transistor has turned on.

17 . The method in accordance with claim 16 , the pre-condition for applying the negative bias voltage being the detection that the transistor has turned off.

18 . The method in accordance with claim 16 , another pre-condition for applying the negative bias voltage being the detection that the transistor has a short.

19 . The method in accordance with claim 14 , the pre-condition for applying the negative bias voltage being the detection that the transistor has turned off.

20 . The method in accordance with claim 19 , another pre-condition for applying the negative bias voltage being the detection that the transistor has a short.