IP Library Granted Patent US 12,562,136
Granted Patent B2
US 12,562,136 · App. 18/916,962 · Granted Feb 24, 2026

Active matrix substrate and display device

Inventor: Yohsuke Fujikawa (Sakai City, JP)
Assignee: SHARP KABUSHIKI KAISHA
G09G3/3648G02F1/1345G02F1/13452G02F1/136286G09G2310/0202
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Quick Facts
Patent No.
US 12,562,136
App. No.
18/916,962
Granted
Feb 24, 2026
Kind
B2
Abstract

An active matrix substrate includes a plurality of signal lines, each of which includes first and second line portions and an inner connection portion (connection portion) that connects the first and second line portions. The first and second line portions of one of two adjacent signal lines are made of first and second conductive layers, respectively, and the first and second line portions of the other of the two adjacent signal lines are made of second and first conductive layers, respectively. The position of the connection portion of each of the signal lines is determined in accordance with the layout position of that signal line in the line region.

Claims (49)

1 . An active matrix substrate comprising:

scan lines extending in a first direction and data lines extending in a second direction intersecting the first direction, the scan lines and the data lines being arranged in a matrix region of the active matrix substrate;

switching elements provided in the matrix region and electrically connected to the data lines and the scan lines, respectively;

terminals provided in a terminal region of the active matrix substrate to input external signals to the data lines;

signal lines provided in a wiring region between the matrix region and the terminal region and electrically connected to the terminals, respectively; and

connection lines provided between the matrix region and the wiring region and electrically connecting at least one of the signal lines; wherein

the connection lines and the signal lines are electrically connected to each other via at least one of a plurality of thin film transistors; and

the signal lines includes a first signal line that includes a first wiring portion made of a first conductive layer and a second wiring portion made of a second conductive layer different from the first conductive layer.

2 . The active matrix substrate according to claim 1 , wherein

the terminals includes a first end terminal and a second end terminal at two ends of the terminals in the first direction;

the signal lines include a first end signal line and a second end signal line at two ends of the signal lines in the first direction;

one end of the first end signal line is electrically connected to one of the plurality of thin film transistors, and another end of the first end signal line is electrically connected to one of the terminals;

one end of the second end signal line is electrically connected to another one of the plurality of thin film transistors, and the other end of the second end signal line is electrically connected to another one of the terminals; and

a distance between the one end of the first end signal line and the one end of the second end signal line is greater than a distance between the first end terminal and the second end terminal.

3 . The active matrix substrate according to claim 2 , wherein

the data lines includes a first end data line and a second end data line at two ends of the data lines in the first direction;

the distance between the one end of the first end signal line and the one end of the second end signal line is smaller than a distance between the first end data line and the second end data line.

4 . The active matrix substrate according to claim 1 , wherein

the signal lines includes a second signal line adjacent to the first signal line;

the second signal line includes a third wiring portion located on the matrix region side of the second signal line and a fourth wiring portion located on the terminal region side of the second signal line;

the first wiring portion is located on the matrix region side of the first signal line and the second wiring portion is located on the terminal region side of the first signal line; and

the fourth wiring portion of the second signal line is made of the first conductive layer, and the third wiring portion of the second signal line is made of the second conductive layer.

5 . The active matrix substrate according to claim 1 , wherein

the connection lines include a first end connection line and a second end connection line at two ends of the connection lines in the first direction; and

the first end connection line and the second end connection line extend in directions different from the first direction and the second direction.

6 . The active matrix substrate according to claim 1 , further comprising:

RBG switch circuits electrically connected to the data lines and the connection lines, respectively; wherein

at least one of the RBG switch circuits is connected to at least two of the data lines and one of the connection lines.

7 . The active matrix substrate according to claim 1 , further comprising:

inspection circuits electrically connected to the connection lines and the signal lines; wherein

at least one of the inspection circuits includes at least one of the plurality of thin film transistors.

8 . The active matrix substrate according to claim 1 , further comprising:

protection circuits electrically connected to the connection lines and the signal lines; wherein

at least one of the protection circuits includes at least one of the plurality of thin film transistors.

9 . The active matrix substrate according to claim 1 , further comprising:

a data driver to output the external signals; wherein

the data driver is connected to the terminals.

10 . The active matrix substrate according to claim 1 , further comprising:

RBG switch circuits electrically connected to the data lines and the connection lines, respectively; and

one of a plurality of inspection circuits and a plurality of protection circuits, which are electrically connected to the connection lines and the signal lines; wherein

at least one of the RBG switch circuits is connected to at least two of the data lines and one of the connection lines;

the one of the plurality of inspection circuits and the plurality of protection circuits includes at least one of the plurality of thin film transistors; and

a length of the one of the plurality of inspection circuits and the plurality of protection circuits in the first direction is smaller than a length of the RBG switch circuits in the first direction.

11 . The active matrix substrate according to claim 10 , wherein

the one of the plurality of inspection circuits and the plurality of protection circuits, and the RBG switch circuits are located between the matrix region and the wiring region.

12 . The active matrix substrate according to claim 10 , wherein

each of the RBG switch circuits is connected to at least two of the data lines and one of the connection lines; and

the one of the plurality of inspection circuits and the plurality of protection circuits is each connected to one of the signal lines and one of the connection lines, respectively.

13 . A display device comprising the active matrix substrate according to claim 1 .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 16, 2024
From: FUJIKAWA, YOHSUKE
To: SHARP KABUSHIKI KAISHA
Reel/Frame 068911/0732 →
Priority Claims (1)
JP 2013-008254 · Jan 21, 2013 · national
Continuity (9)
Continuation 18212828 · Jun 22, 2023
Continuation 17866762 · Jul 18, 2022
Continuation 17345020 · Jun 11, 2021
Continuation 16831877 · Mar 27, 2020
Continuation 16455830 · Jun 28, 2019
Continuation 16059080 · Aug 9, 2018
Continuation 15832850 · Dec 6, 2017
Continuation 14761349
Related Publication 20250037676A1 · Jan 30, 2025
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