Granted Patent B2

US 12,469,455 · App. 18/922,578 · Granted Nov 11, 2025

Inventors: Sehyuk Park (Yongin-si, KR); Hongsoo Kim (Yongin-si, KR); Jin-Wook Yang (Yongin-si, KR)

Assignee: SAMSUNG DISPLAY CO., LTD.

G09G3/3233G09G3/2003G09G2300/0426G09G2300/0452G09G2310/0297G09G2310/08G09G2330/021

Abstract

Claims (71)

1 . A display device comprising:

a plurality of data lines arranged in a first direction;

a demultiplexer connected to the plurality of data lines;

a plurality of first gate lines arranged in a second direction;

a plurality of second gate lines arranged in the second direction; and

a plurality of pixels, each of which is connected to one corresponding data line among the plurality of data lines and one corresponding gate line among the plurality of first gate lines and the plurality of second gate lines, the plurality of pixels including a first group of pixels and a second group of pixels,

wherein the plurality of data lines includes a first group of data lines connected to the first group of pixels and a second group of data lines connected to the second group of pixels,

wherein a data signal is provided to the first group of pixels in a first sub-frame period of one frame period, and

wherein a data signal is provided to the second group of pixels in a second sub-frame period of the one frame period that is adjacent to the first sub-frame period,

wherein the demultiplexer includes a plurality of first control transistors connected to the first group of data lines in a one-to-one correspondence and a plurality of second control transistors connected to the second group of data lines in a one-to-one correspondence,

wherein in the first sub-frame period, a first control signal that controls a plurality of first control transistors has activation levels and inactivation levels alternating with one another, and a second control signal that controls a plurality of second control transistors has an inactivation level throughout an entirety of the first sub-frame period, and

wherein in the second sub-frame period, the second control signal has activation levels and inactivation levels alternating with one another, and the first control signal has an inactivation level throughout an entirety of the second sub-frame period.

2 . The display device of claim 1 , wherein the plurality of first gate lines and the plurality of second gate lines alternate with one another in the second direction,

wherein the plurality of first gate lines are sequentially activated in the first sub-frame period, and

wherein the plurality of second gate lines are sequentially activated in the second sub-frame period.

3 . The display device of claim 1 , further comprising:

wherein the plurality of first control transistors are configured to be controlled by the first control signal provided through a first control line, and

wherein the plurality of second control transistors are configured to be controlled by a second control signal provided through the second control line.

4 . The display device of claim 1 , wherein the plurality of pixels includes a first pixel configured to output light having a first color, a second pixel configured to output light having a second color different from the first color, a third pixel configured to output light having a third color different from the first color and the second color, and a fourth pixel configured to output light having the second color,

wherein the first pixel and the third pixel are alternately arranged one by one in the first direction and the second direction, and

wherein the second pixel and the fourth pixel are alternately arranged one by one in the first direction and the second direction.

5 . The display device of claim 4 , wherein the first group of pixels include the first pixel and the third pixel, and

wherein the second group of pixels include the second pixel and the fourth pixel.

6 . The display device of claim 5 , wherein each of the first pixel and the third pixel is electrically connected to a corresponding first gate line among the plurality of first gate lines, and

wherein each of the second pixel and the fourth pixel is electrically connected to a corresponding second gate line among the plurality of second gate lines.

7 . The display device of claim 5 , wherein the first group of data lines is connected to the first pixel and the third pixel, respectively, and the second group of data lines is connected to the second pixel and the fourth pixel, respectively, and

wherein the first group of data lines and the second group of data lines alternate with one another.

8 . The display device of claim 5 , wherein the first group of data lines includes a first-first group data line connected to the first pixel and a first-second group data line connected to the third pixel,

wherein the second group of data lines is connected to the second pixel and the fourth pixel, respectively, and

wherein the first-first group data line, one of the second group of data lines, the first-second group data line, and another one of the second group of data lines are sequentially arranged.

9 . The display device of claim 4 , wherein the first group of data lines includes a first-first group data line connected to the first pixel and the third pixel and a first-second group data line connected to the second pixel and the fourth pixel,

wherein the second group of data lines includes a second-first group data line connected to the second pixel and the fourth pixel and a second-second group data line connected to the first pixel and the third pixel, and

wherein the first-first group data line, the second-first group data line, the second-second group data line, and the first-second group data line are sequentially arranged.

10 . The display device of claim 4 , wherein the first group of data lines includes a first-first group data line connected to the first pixel, a first-second group data line connected to the second pixel and the fourth pixel, and a first-third group data line connected to the third pixel,

wherein the second group of data lines includes a second-first group data line connected to the third pixel, a second-second group data line connected to the second pixel and the fourth pixel, and a second-third group data line connected to the first pixel, and

wherein the first-first group data line, the second-first group data line, the first-second group data line, the second-second group data line, the second-third group data line, the first-third group data line, the second-second group data line, and the first-second group data line are sequentially arranged.

11 . The display device of claim 4 , wherein the first group of data lines includes a first-first group data line connected to the first pixel, a first-second group data line connected to the third pixel, and a first-third group data line connected to the second pixel and the fourth pixel,

wherein the second group of data lines includes a second-first group data line connected to the second pixel and the fourth pixel, a second-second group data line connected to the first pixel, and a second-third group data line connected to the third pixel, and

wherein the first-first group data line, the second-first group data line, the first-second group data line, the second-first group data line, the second-second group data line, the first-third group data line, the second-third group data line, and the first-third group data line are sequentially arranged.

12 . The display device of claim 4 , wherein the first group of data lines includes a first-first group data line connected to the first pixel, a first-second group data line connected to the third pixel, and a first-third group data line connected to the second pixel and the fourth pixel,

wherein the second group of data lines includes a second-first group data line connected to the second pixel and the fourth pixel, a second-second group data line connected to the first pixel, and a second-third group data line connected to the third pixel, and

wherein the first-first group data line, the first-second group data line, the second-first group data line, the second-first group data line, the second-second group data line, the second-third group data line, the first-third group data line, and the first-third group data line are sequentially arranged.

13 . The display device of claim 4 , wherein the first pixel and the third pixel are configured to emit light in the first sub-frame period, and the second pixel and the fourth pixel are configured to emit light in the second sub-frame period.

14 . The display device of claim 4 , wherein the first pixel, the second pixel, the third pixel, and the fourth pixel are configured to emit light in the first sub-frame period and the second sub-frame period.

15 . A display device comprising:

a plurality of first data lines arranged in a first direction;

a plurality of second data lines arranged in the first direction;

a plurality of gate lines arranged in a second direction;

a plurality of first pixels electrically connected to the plurality of first data lines and the plurality of gate lines;

a plurality of second pixels electrically connected to the plurality of second data lines and the plurality of gate lines; and

a demultiplexer including a plurality of first control transistors connected to the plurality of first data lines in a one-to-one correspondence and a plurality of second control transistors connected to the plurality of second data lines in a one-to-one correspondence,

wherein in a first sub-frame period of one frame period, a first control signal to control the plurality of first control transistors has activations levels and inactivation levels alternating with one another, and a second control signal to control the plurality of second control transistors has an inactivation level throughout an entirety of the first sub-frame period, and

wherein in a second sub-frame period of the one frame period that is adjacent to the first sub-frame period, the second control signal has activation levels and inactivation levels alternating with one another, and the first control signal has an inactivation level throughout an entirety of the second sub-frame period.

16 . The display device of claim 15 , wherein the plurality of gate lines includes a plurality of first gate lines electrically connected to the plurality of first pixels and a plurality of second gate lines electrically connected to the plurality of second pixels, and

wherein the plurality of first gate lines are sequentially activated in the first sub-frame period, and

wherein the plurality of second gate lines are sequentially activated in the second sub-frame period.

17 . The display device of claim 16 , wherein the plurality of first pixels and the plurality of second pixels include a first pixel configured to output light having a first color, a second pixel configured to output light having a second color different from the first color, a third pixel configured to output light having a third color different from the first color and the second color, and a fourth pixel configured to output light having the second color, and

wherein the first to fourth pixels are configured to emit light in the one frame period.

18 . The display device of claim 17 , wherein the first pixel and the third pixel are configured to emit light in the first sub-frame period, and the second pixel and the fourth pixel are configured to emit light in the second sub-frame period, and

wherein the first pixel, the second pixel, the third pixel, and the fourth pixel are configured to emit light in the first sub-frame period and the second sub-frame period.

19 . An electronic device comprising:

a display device comprising:

a plurality of data lines arranged in a first direction;

a plurality of gate lines arranged in a second direction;

a plurality of pixels electrically connected to the plurality of data lines and the plurality of gate lines;

a plurality of first control transistors connected to some of the plurality of data lines in a one-to-one correspondence; and

a plurality of second control transistors connected to the other data lines among the plurality of data lines in a one-to-one correspondence,

wherein a data signal is provided only to the some data lines connected to the plurality of first control transistors in a first sub-frame period of one frame period, and

wherein a data signal is provided only to the other data lines connected to the plurality of second control transistors in a second sub-frame period of the one frame period that is adjacent to the first sub-frame period,

wherein in the first sub-frame period, a first control signal that controls the plurality of first control transistors has activation levels and inactivation levels alternating with one another, and a second control signal that controls the plurality of second control transistors has an inactivation level throughout an entirety of the first sub-frame period, and

wherein in the second sub-frame period, the second control signal has activation levels and inactivation levels alternating with one another, and the first control signal has an inactivation level throughout an entirety of the second sub-frame period.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (42)