MULTIPLYING ACCUMULATION WITH SHIFTING BASED ON MAXIMUM MANTISSA PRODUCT BITLENGTH
A device, such as a multiplying accumulator or at-memory or single instruction, multiple data (SIMD) processing element, is configured to receive numbers defined by an encoding that specifies mantissa and exponent. A product of the mantissas is computed. The product is left shifter by a sum of the exponents and a selectable shift to obtain a left-shifted product. The selectable shift may be based on a selectable radix point, exponent biases, and a maximum mantissa product bitlength. Products may be accumulated. Left-shifted product, whether an intermediate or final result, may be right-shifter by a number of bits that is based on the maximum mantissa product bitlength.
1 . A device comprising:
circuitry configured to:
receive a first number defined by a first mantissa and a first exponent;
receive a second number defined by a second mantissa and a second exponent;
receive a selectable shift;
compute a product of the first mantissa and the second mantissa;
left shift the product by a sum of the first exponent, the second exponent, and the selectable shift to obtain a left-shifted product; and
right shift the left-shifted product by a number of bits that is based on a maximum mantissa product bitlength to obtain a right-shifted product.
2 . The device of claim 1 , wherein the circuitry is configured to accumulate the right-shifted product.
3 . The device of claim 1 , wherein the circuitry is configured to accumulate the left-shifted product for a number of multiplications and left shifts before performing the right shift.
4 . The device of claim 1 , wherein the selectable shift is based on a selectable radix point, a first bias of the first exponent, and a second bias of the second exponent.
5 . The device of claim 4 , wherein the selectable shift is the selectable radix point minus a sum of the first bias and the second bias.
6 . The device of claim 4 , wherein the selectable shift is fixed for a sequence of multiplying accumulations performed with a sequence of received first and second numbers.
7 . The device of claim 1 , wherein the number of bits is the maximum mantissa product bitlength minus one.
8 . The device of claim 1 , wherein:
the number of bits is the maximum mantissa product bitlength minus two; and
the circuitry is further configured to round the right-shifted product by incrementing the right-shifted product by one and further right shifting the right-shifted product by one bit.
9 . The device of claim 1 , wherein:
the first number is further defined by a first sign bit;
the second number is further defined by a second sign bit; and
the circuitry is further configured to apply the first sign bit and the second sign bit to the left-shifter product or the right-shifted product.
10 . A circuit comprising:
a multiplier to multiply mantissas of binary numbers and output a mantissa product;
a shifter to left shift the mantissa product by a number of bits determined from exponents of the binary numbers and a maximum mantissa product bitlength that is storable to obtain an intermediate result;
an accumulator to accumulate the intermediate result to obtain a final result and output the final result.
11 . The circuit of claim 10 , wherein the shifter is further to right shift the intermediate result based on the maximum mantissa product bitlength.
12 . The circuit of claim 10 , wherein the final result is right shifter based on the maximum mantissa product bitlength.
13 . The circuit of claim 10 , further comprising another shifter to right shift the final result based on the maximum mantissa product bitlength.
14 . The circuit of claim 10 , wherein the shifter is to left shift the mantissa product further by a selectable radix point.
15 . The circuit of claim 10 , wherein the shifter is to left shift the mantissa product further by biases of the exponents.
16 . A device comprising:
a controller; and
an array of processing elements configured with the controller for single instruction, multiple data operation, each processing element including a multiplying accumulator configured to:
multiply mantissas of binary numbers and output a mantissa product;
left shift the mantissa product by a number of bits determined from exponents of the binary numbers and a maximum mantissa product bitlength that is storable to obtain an intermediate result; and
accumulate the intermediate result to obtain a final result and output the final result.
17 . The device of claim 16 , wherein the multiplying accumulator is further configured to right shift the intermediate result based on the maximum mantissa product bitlength.
18 . The device of claim 16 , wherein the multiplying accumulator is further configured to right shift the final result based on the maximum mantissa product bitlength.
19 . The device of claim 16 , wherein the controller is configured to right shift the final result based on the maximum mantissa product bitlength.
20 . The device of claim 16 , wherein the controller is connectable to a host system that is configured to right shift the final result based on the maximum mantissa product bitlength.