TUNING COUPLING STRENGTH BETWEEN CONTROL LINES AND QUANTUM CIRCUIT DEVICES IN SUPERCONDUCTING QUANTUM PROCESSORS

1 . A method comprising:

identifying a design of first and second quantum processor wafers of a quantum processing system, the first quantum processor wafer comprising a qubit device, the qubit device comprising two qubit electrodes and a SQUID loop connected between the two qubit electrodes, the second quantum processor wafer comprising a control line configured to apply control signals to the qubit device, the control line comprising:

first and second control ports;

a circuit loop inductively coupled to the SQUID loop; and

conductive traces connected between the circuit loop and the respective first and second control ports, the conductive traces being capacitively coupled to the two qubit electrodes;

obtaining simulation data from simulations of the quantum processing system based on the design;

obtaining experimental data from measurements of the quantum processing system manufactured according to the design; and

modifying the design of the second quantum processor wafer based on the simulation data and the experimental data, wherein modifying the design comprises modifying a differential capacitance between the control line and the two qubit electrodes based on one or more predefined constraints.

2 . The method of claim 1 , wherein the one or more predefined constraints comprise at least one of:

a coherence time,

a gate time, or

an energy loss.

3 . The method of claim 1 , wherein each of the first and second control ports comprises a superconducting through-hole via extending from a first surface to a second, opposite surface of the second quantum processor wafer.

4 . The method of claim 1 , wherein modifying the differential capacitance comprises modifying a geometry of one or more of the conductive traces.

5 . The method of claim 1 , wherein modifying the differential capacitance comprises at least one of:

modifying a length of one or more of the conductive traces; or modifying an angle of one or more turns in one or more of the conductive traces.

6 . The method of claim 1 , wherein:

each of the conductive traces comprises:

a first section that extends in a first direction from a control port toward the circuit loop;

a second section that extends in a second direction from the control loop toward one of the two qubit electrodes, wherein the second direction is perpendicular to the first direction; and

an intermediate section that connects the first and second sections; and

wherein modifying the differential capacitance comprises:

modifying lengths of one or more sections of the conductive traces; and

modifying an orientation of the intermediate sections relative to the first and second sections.

7 . The method of claim 1 , wherein modifying the differential capacitance comprises at least one of:

adding one or more transmission line branches to the control line of the second quantum processor wafer; or

modifying one or more transmission line branches extending from the control line of the second quantum processor wafer.

8 . The method of claim 1 , wherein modifying the differential capacitance comprises at least one of:

adding one or more transmission line branches to the qubit device on the first quantum processor wafer; or

modifying one or more transmission line branches extending from the qubit device of the first quantum processor wafer.

9 . The method of claim 1 , wherein the differential capacitance is a first differential capacitance, the qubit device is a first qubit device, the first quantum processor wafer comprises a second qubit device communicably coupled to the first qubit device, the second qubit device comprises two respective qubit electrodes, and modifying the design comprises modifying a second differential capacitance between the control line and one of the two respective qubit electrodes of the second qubit device.

10 . The method of claim 1 , wherein obtaining experimental data comprises:

determining a Purcell limited relaxation rate of the qubit device based on the simulation data and the measurements.

11 . The method of claim 10 , wherein determining the Purcell limited relaxation rate of the qubit device comprises:

determining drivability and decoherence time for a specific qubit frequency and control line design;

determining a minimum relaxation time; and

determining an update value of the drivability based on a predefined criterion.

12 . The method of claim 11 , wherein the predefined criterion comprises a tradeoff between relaxation rate and gate performance.

13 . A computing system comprising:

one or more processors; and

memory storing instructions configured to perform operations when executed by the one or more processors, the operations comprising:

identifying a design of first and second quantum processor wafers of a quantum processing system, the first quantum processor wafer comprising a qubit device, the qubit device comprising two qubit electrodes and a superconducting quantum interference device (SQUID) loop connected between the two qubit electrodes, the second quantum processor wafer comprising a control line configured to apply control signals to the qubit device, the control line comprising:

first and second control ports;

a circuit loop inductively coupled to the SQUID loop; and

conductive traces connected between the circuit loop and the respective first and second control ports, the conductive traces control lines being capacitively coupled to the two qubit electrodes;

obtaining simulation data from numerical simulations of the quantum processing system based on the design;

obtaining experimental data based on measurements of the quantum processing system manufactured according to the design; and

modifying the design of the second quantum processor wafer based on the simulation data and the experimental data, wherein modifying the design comprises modifying a differential capacitance between the control line and the two qubit electrodes based on one or more predefined constraints.

14 . The system of claim 13 , wherein the one or more predefined constraints comprise at least one of:

a coherence time,

a gate time, or

an energy loss.

15 . The system of claim 13 , wherein each of the first and second control ports comprises a superconducting through-hole via extending from a first surface to a second opposite surface of the second quantum processor wafer.

16 . The system of claim 13 , wherein modifying the differential capacitance comprises modifying a geometry of one or more of the conductive traces.

17 . The system of claim 13 , wherein modifying the differential capacitance comprises at least one of:

modifying a length of one or more of the conductive traces; or

modifying an angle of one or more turns in one or more of the conductive traces.

18 . The system of claim 13 , wherein:

each of the conductive traces comprises:

a first section that extends in a first direction from a control port toward the circuit loop;

a second section that extends in a second direction from the control loop toward one of the two qubit electrodes, wherein the second direction is perpendicular to the first direction; and

an intermediate section that connects the first and second sections; and

wherein modifying the differential capacitance comprises:

modifying lengths of one or more sections of the conductive traces; and

modifying an orientation of the intermediate sections relative to the first and second sections.

19 . The system of claim 13 , wherein modifying the differential capacitance comprises at least one of:

adding one or more transmission line branches to one or more of the conductive traces; or

modifying one or more transmission line branches extending from one or more of the conductive traces.

20 . The system of claim 13 , wherein modifying the differential capacitance comprises at least one of:

adding one or more transmission line branches to the qubit device of the first quantum processor wafer; or

modifying one or more transmission line branches extending from the qubit device of the first quantum processor wafer.

21 . The system of claim 13 , wherein the differential capacitance is a first differential capacitance, the qubit device is a first qubit device, the first quantum processor wafer comprises a second qubit device communicably coupled to the first qubit device, the second qubit device comprises two respective qubit electrodes, and modifying the design comprises modifying a second differential capacitance between the control line and one of the two respective qubit electrodes of the second qubit device.

22 . The system of claim 13 , wherein obtaining experimental data comprises:

determining a Purcell limited relaxation rate of the qubit device based on the simulation data and the experimental data.

23 . The system of claim 22 , wherein determining the Purcell limited relaxation rate of the qubit device comprises:

determining drivability and decoherence time for a specific qubit frequency and control line design;

determining a minimum relaxation time; and

determining an update value of the drivability based on a predefined criterion.

24 . The system of claim 23 , wherein the predefined criterion comprises a tradeoff between relaxation rate and gate performance.

25 - 38 . (canceled)