Granted Patent B1

US 12,541,313 · App. 18/930,466 · Granted Feb 3, 2026

Inventor: Xin Liang (San Jose, CA)

Assignee: Pure Storage, Inc.

G06F3/0634G06F3/061G06F3/0679

Abstract

Claims (52)

1 . A method comprising:

determining, by a storage controller, an interrupt time window based on a set of factors;

receiving, by the storage controller, a first interrupt from a storage resource;

providing, by the storage controller, the first interrupt to a processor for waking up an I/O thread to process I/O operations from an I/O queue;

receiving, by the storage controller, a second interrupt from the storage resource;

determining, by the storage controller, that the second interrupt is received within the interrupt time window following the first interrupt;

disabling, by the storage controller based on the interrupt time window, the second interrupt;

receiving, by the storage controller, a third interrupt from the storage resource;

determining, by the storage controller, that the third interrupt is received within the interrupt time window following the second interrupt; and

forgoing, by the storage controller, disabling of the third interrupt based on a number of running I/O threads.

2 . The method of claim 1 , wherein the set of factors comprises one or more of a number of inactive I/O threads or a latency rate for I/O requests.

3 . The method of claim 1 , further comprising:

determining, by the storage controller, updated values for the set of factors; and

adjusting, by the storage controller, the interrupt time window based on the updated values.

4 . The method of claim 3 , wherein the interrupt time window is adjusted after each received interrupt.

5 . The method of claim 1 , further comprising waking up, by the storage controller, one or more inactive I/O threads based on an additional set of factors.

6 . The method of claim 5 , wherein the additional set of factors comprises one or more of a latency rate for I/O requests or a number of inactive I/O threads.

7 . The method of claim 1 , wherein the disabling the second interrupt comprises masking an interrupt vector associated with the storage resource.

8 . The method of claim 1 , wherein the disabling the second interrupt comprises disabling incoming interrupts from the storage resource.

9 . The method of claim 8 , further comprising re-enabling the incoming interrupts from the storage resource when the interrupt time window lapses.

10 . The method of claim 1 , further comprising calculating a set of running values for the set of factors;

wherein the determining the interrupt time window is based on the set of running values.

11 . The method of claim 1 , wherein the storage resource comprises an NVMe device, and wherein the storage controller comprises a UNVMe tool.

12 . A system comprising:

a memory storing instructions; and

one or more processors communicatively coupled to the memory and configured to execute the instructions to perform a process comprising:

determining an interrupt time window based on a set of factors;

receiving a first interrupt from a storage resource;

providing the first interrupt to a processor for waking up an I/O thread to process I/O operations from an I/O queue;

receiving a second interrupt from the storage resource;

determining that the second interrupt is received within the interrupt time window following the first interrupt;

disabling, based on the interrupt time window, the second interrupt;

receiving a third interrupt from the storage resource;

determining that the third interrupt is received within the interrupt time window following the second interrupt; and

forgoing disabling of the third interrupt based on a number of running I/O threads.

13 . The system of claim 12 , wherein the set of factors comprises one or more of a number of inactive I/O threads or a latency rate for I/O requests.

14 . The system of claim 12 , wherein the process further comprises:

determining updated values for the set of factors; and

adjusting the interrupt time window based on the updated values.

15 . The system of claim 12 , wherein the process further comprises waking up one or more inactive I/O threads based on an additional set of factors.

16 . The system of claim 12 , wherein the disabling the second interrupt comprises masking an interrupt vector associated with the storage resource.

17 . The system of claim 12 , wherein the storage resource comprises an NVMe device.

18 . A computer program product embodied in a non-transitory computer readable storage medium and comprising computer instructions for:

determining an interrupt time window based on a set of factors;

receiving a first interrupt from a storage resource;

providing the first interrupt to a processor for waking up an I/O thread to process I/O operations from an I/O queue;

receiving a second interrupt from the storage resource;

determining that the second interrupt is received within the interrupt time window following the first interrupt;

disabling, based on the interrupt time window, the second interrupt;

receiving a third interrupt from the storage resource;

determining that the third interrupt is received within the interrupt time window following the second interrupt; and

forgoing disabling of the third interrupt based on a number of running I/O threads.

Assignments (1)

References Cited (44)