FUNCTIONS TO IMPLEMENT TARGET MAPPINGS ON COMPUTING DEVICES
A processor is configured to partition a target mapping of a target function into ranges. Candidate functions are fit to the ranges, such that a candidate function is fit to each range. The candidate functions and the ranges are adjusted based on a cost function. The cost function computes a processing load to execute the candidate functions with the ranges using an array of single instruction, multiple data (SIMD) processing elements. The processor selects the candidate functions and the ranges that minimize the cost function as operational functions and operational ranges that implement the target mapping.
1 . A non-transitory machine-readable medium comprising instructions that, when executed by a processor, cause the processor to:
partition a target mapping of a target function into ranges;
fit candidate functions to the ranges, wherein a candidate function is fit to each range;
adjust the candidate functions and the ranges based on a cost function, wherein the cost function computes a processing load to execute the candidate functions with the ranges using an array of single instruction, multiple data (SIMD) processing elements; and
select the candidate functions and the ranges that minimize the cost function as operational functions and operational ranges that implement the target mapping.
2 . The non-transitory machine-readable medium of claim 1 , wherein the instructions are to adjust the candidate functions and the ranges to minimize the cost function.
3 . The non-transitory machine-readable medium of claim 1 , wherein the instructions are to adjust a coefficient of a candidate function.
4 . The non-transitory machine-readable medium of claim 1 , wherein the instructions are to select the candidate functions from a predefined set of primitive functions including:
a constant;
a linear function;
a quadratic function; and
a binary indexing function.
5 . The non-transitory machine-readable medium of claim 1 , wherein the cost function computes a number of cycles to execute the candidate functions with the ranges.
6 . The non-transitory machine-readable medium of claim 1 , wherein the ranges are non-overlapping.
7 . A computing device comprising:
memory; and
a processor connected to the memory, the processor configured to:
partition a target mapping of a target function into ranges;
fit candidate functions to the ranges, wherein a candidate function is fit to each range;
adjust the candidate functions and the ranges based on a cost function, wherein the cost function computes a processing load to execute the candidate functions with the ranges using an array of single instruction, multiple data (SIMD) processing elements; and
select the candidate functions and the ranges that minimize the cost function as operational functions and operational ranges that implement the target mapping.
8 . The device of claim 7 , wherein the processor is configured to adjust the candidate functions and the ranges to minimize the cost function.
9 . The device of claim 7 , wherein the processor is configured to adjust a coefficient of a candidate function.
10 . The device of claim 7 , wherein the processor is configured to select the candidate functions from a predefined set of primitive functions including:
a constant;
a linear function;
a quadratic function; and
a binary indexing function.
11 . The device of claim 7 , wherein the cost function computes a number of cycles to execute the candidate functions with the ranges.
12 . The device of claim 7 , wherein the ranges are non-overlapping.
13 . The device of claim 7 , further comprising an external interface configured to load a representation of the operational functions and operational ranges onto a SIMD computing device.