IP Library Patent Application 18937960
Patent Application
App. No. 18/937,960

CLASSIFYING COMPARATORS BASED ON COMPARATOR OFFSETS

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Quick Facts
Patent No.
US None
App. No.
18/937,960
Abstract

Various embodiments relate to classifying comparators based on comparator offsets. A method may include applying, via a strobe, a first voltage to each of a first input and a second input of a comparator to generate a number of output signals from the comparator, wherein each output signal has one of a first polarity and a second polarity. The method may further include in response to each of the number of output signals being the first polarity, applying, via a strobe, an external offset voltage having the second polarity to the comparator to generate a second number of output signals. Further, the method may include in response to each of the second number of output signals being the same polarity, identifying the comparator as a reliable comparator.

Claims (26)

1 . A method, comprising:

for respective comparators:

repeatedly strobing a comparator with a first voltage at both of a first input and a second input of the comparator to generate first output signals from the comparator, each output signal of the first output signals exhibiting one of a first polarity or a second polarity;

in response to determining that each and every output signal of the first output signals generated from the comparator exhibiting the first polarity, repeatedly strobing the comparator with an external offset voltage exhibiting the second polarity to generate second output signals from the comparator; and

in response to determining that each and every output signal of the second output signals generated from the comparator are exhibiting the first polarity, identifying the comparator as reliable; and

generating a key via reliable comparators.

2 . The method of claim 1 , wherein the generating the key comprises generating respective bits of the key via respective reliable comparators.

3 . The method of claim 1 , comprising utilizing the key for at least one of encrypting data or decrypting data.

4 . The method of claim 1 , wherein the generating the key via reliable comparators comprises generating the key via at least the comparator identified as reliable.

5 . The method of claim 1 , comprising determining that each and every output signal of the second output signals generated from the comparator are exhibiting the first polarity in response to each and every output signal exhibiting a positive polarity or each and every output signal exhibiting a negative polarity.

6 . An apparatus, comprising:

at least one processor; and

a non-transitory computer-readable media to store instructions that, when executed by the at least one processor, enable the at least one processor to:

for respective comparators:

repeatedly strobe a comparator with a first voltage at both of a first input and a second input of the comparator to generate first output signals from the comparator, each output signal of the first output signals exhibits one of a first polarity or a second polarity;

in response to a determination that each and every output signal of the first output signals generated from the comparator exhibits the first polarity, repeatedly strobe the comparator with an external offset voltage exhibiting the second polarity to generate second output signals from the comparator; and

in response to a determination that each and every output signal of the second output signals generated from the comparator exhibits the first polarity, identify the comparator as reliable; and

generate a key via reliable comparators.

7 . The apparatus of claim 6 , wherein the non-transitory computer-readable media to store instructions that, when executed by the at least one processor, enable the at least one processor to:

generate respective bits of the key via respective reliable comparators.

8 . The apparatus of claim 6 , wherein the non-transitory computer-readable media to store instructions that, when executed by the at least one processor, enable the at least one processor to:

utilize the key for at least one of encrypting data or decrypting data.

9 . The apparatus of claim 6 , wherein the non-transitory computer-readable media to store instructions that, when executed by the at least one processor, enable the at least one processor to:

generate the key via at least the comparator identified as reliable.

10 . The apparatus of claim 1 , wherein the non-transitory computer-readable media to store instructions that, when executed by the at least one processor, enable the at least one processor to:

determine that each and every output signal of the second output signals generated from the comparator exhibits the first polarity in response to each and every output signal exhibiting a positive polarity or each and every output signal exhibiting a negative polarity.