Methods for Gather/Scatter Operations in a Vector Processor

1 . A method comprising:

(a) checking for a read port start signal and when received setting an increment count to zero;

(b) initiating a memory read using a port's address register, and setting the increment count to increment count+1;

(c) incrementing the port's address register by a port's stride register;

(d) checking to see if the increment count is greater than or equal to a port's length register and when not so proceeding to (b); and

(e) checking to see if the increment count is greater than or equal to a port's length register and when so proceeding to (a).

2 . The method of claim 1 comprising at (e) resetting the port's address register to an original value.

3 . A method comprising:

(a) receiving a logical address and determining from the logical address a memory bank address and a memory physical address;

(b) using the memory bank address to enable reading from a memory bank;

(c) driving the memory physical address to all memory for reading;

(d) checking to see if the if reading returned valid data and when so, capturing all memory data that has been read out;

(e) rotating the memory data that has been read by 32 times the bank address; and

(f) driving bits 31:0 to an arithmetic logic unit.

4 . The method of claim 3 comprising at (c) incrementing the memory physical address by a stride value.

5 . A method comprising:

determining a bank identification and a random access memory physical address from a logical address;

driving the random access memory physical address to all the random access memory;

capturing a 32 bit result from an arithmetic unit;

rotating the captured 32 result based on the bank identification;

driving the rotated 32 bit result to all banks of the random access memory; and

activating a write enable of the random access memory based on the bank identification.

6 . The method of claim 5 comprising incrementing a write port address by a write stride value.