CONFIGURABLE CACHE FOR COHERENT SYSTEM
A device includes a memory bank. The memory bank includes data portions of a first way group. The data portions of the first way group include a data portion of a first way of the first way group and a data portion of a second way of the first way group. The memory bank further includes data portions of a second way group. The device further includes a configuration register and a controller configured to individually allocate, based on one or more settings in the configuration register, the first way and the second way to one of an addressable memory space and a data cache.
1 . A device comprising:
a controller configurable to receive an access request including a memory address from a peripheral; and
a cache configuration register coupled to the controller and configured to store a first mask bit associated with the peripheral,
wherein the controller is configurable to:
perform a first logical operation with a first pointer bit and the first mask bit to generate a first output bit; and
allocate a cache way to a cache tag associated with the memory address using the first output bit.
2 . The device of claim 1 , wherein the controller is configurable to allocate the cache way to the cache tag using the first output bit and a second pointer bit.
3 . The device of claim 2 ,
wherein the first pointer bit is a least significant bit of a pointer, and
wherein the second pointer bit is a most significant bit of the pointer.
4 . The device of claim 1 , wherein the controller is configurable to:
retrieve a second mask bit from the cache configuration register;
perform the first logical operation with a second pointer bit and the second mask bit to generate a second output bit; and
allocate the cache way to the cache tag using the first output bit and the second output bit.
5 . The device of claim 4 ,
wherein the first pointer bit is a first least significant bit of a pointer,
wherein the second pointer bit is a second least significant bit of the pointer,
wherein the pointer further includes a most significant pointer bit, and
wherein the controller is configurable to allocate the cache way to the cache tag using the first output bit, the second output bit, and the most significant pointer bit.
6 . The device of claim 5 ,
wherein the most significant pointer bit is a first most significant pointer bit,
wherein the pointer further includes a second most significant pointer bit, and
wherein the controller is configurable to allocate the cache way to the cache tag using the first output bit, the second output bit, the first most significant pointer bit, and the second most significant pointer bit.
7 . The device of claim 1 ,
wherein the cache configuration register is configured to store the first mask bit associated with a membership of the peripheral, and
wherein the membership of the peripheral indicates whether the peripheral is associated with a real-time priority or a non-real-time priority.
8 . The device of claim 1 ,
wherein the cache configuration register is configured to store a second mask bit associated with the peripheral, and
wherein the controller is configurable to:
perform a second logical operation with the first output bit and the second mask bit to generate a first identifier bit; and
allocate the cache way to the cache tag using the first identifier bit.
9 . The device of claim 8 ,
wherein the cache configuration register is configured to:
store a third mask bit associated with the peripheral; and
store a fourth mask bit associated with the peripheral, and
wherein the controller is configurable to:
perform the first logical operation with a second pointer bit and the third mask bit to generate a second output bit;
perform the second logical operation with the second output bit and the fourth mask bit to generate a second identifier bit; and
allocate the cache way to the cache tag using the first identifier bit and the second identifier bit.
10 . The device of claim 1 ,
wherein the first mask bit is a bit in an AND mask, and
wherein the first logical operation is an AND operation.
11 . The device of claim 1 ,
wherein the first mask bit is a bit in an OR mask, and
wherein the first logical operation is an OR operation.
12 . The device of claim 1 , wherein the first pointer bit is a bit in a randomly generated pointer.
13 . A method comprising:
receiving an access request including a memory address from a peripheral;
retrieving a first mask bit associated with the peripheral from a cache configuration register;
performing a first logical operation with a first pointer bit and the first mask bit to generate a first output bit; and
allocating a cache way to a cache tag associated with the memory address using the first output bit.
14 . The method of claim 13 , further comprising:
retrieving a second mask bit associated with the peripheral from the cache configuration register;
performing the first logical operation with a second pointer bit and the second mask bit to generate a second output bit; and
allocating the cache way to the cache tag using the first output bit and the second output bit.
15 . The method of claim 14 ,
wherein the first pointer bit is a first least significant bit of a pointer,
wherein the second pointer bit is a second least significant bit of the pointer,
wherein the pointer further includes a most significant pointer bit, and
wherein the method further comprises allocating the cache way to the cache tag using the first output bit, the second output bit, and the most significant pointer bit.
16 . The method of claim 15 ,
wherein the most significant pointer bit is a first most significant pointer bit,
wherein the pointer further includes a second most significant pointer bit, and
wherein the method further comprises allocating the cache way to the cache tag using the first output bit, the second output bit, the first most significant pointer bit, and the second most significant pointer bit.
17 . The method of claim 13 , further comprising:
retrieving a second mask bit associated with the peripheral from the cache configuration register;
performing a second logical operation with the first output bit and the second mask bit to generate a first identifier bit; and
allocating the cache way to the cache tag using the first identifier bit.
18 . The method of claim 17 , further comprising:
retrieving a third mask bit associated with the peripheral from the cache configuration register;
retrieving a fourth mask bit associated with the peripheral from the cache configuration register;
performing the first logical operation with a second pointer bit and the third mask bit to generate a second output bit;
performing the second logical operation with the second output bit and the fourth mask bit to generate a second identifier bit; and
allocating the cache way to the cache tag using the first identifier bit and the second identifier bit.
19 . A system comprising:
a memory cache including a cache way;
a peripheral;
a cache controller configurable to receive an access request including a memory address from the peripheral; and
a cache configuration register coupled to the cache controller and configured to store a first mask bit associated with the peripheral,
wherein the cache controller is configurable to:
perform a first logical operation with a first pointer bit and the first mask bit to generate a first output bit; and
allocate the cache way to a cache tag associated with the memory address using the first output bit.
20 . The system of claim 19 ,
wherein the cache configuration register is configured to store a second mask bit associated with the peripheral, and
wherein the cache controller is configurable to:
perform a second logical operation with the first output bit and the second mask bit to generate a first identifier bit; and
allocate the cache way to the cache tag using the first identifier bit.