Digital equalization adaptation with partially unscrambled data

1 . A Peripheral Component Interconnect Express (PCIE) receiver comprising:

an analog to digital converter (ADC);

an equalizer; and

one or more processors configured to perform operations comprising:

accessing a training sequence comprising a plurality of unscrambled portions interleaved with a plurality of scrambled portions;

instructing the ADC to sample the training sequence to generate a first set of digital symbols representing the plurality of unscrambled portions and the plurality of scrambled portions to the equalizer;

causing the ADC to periodically slip sampling of the training sequence to generate a second set of digital symbols in which the plurality of unscrambled portions of the training sequence are randomized; and

training one or more coefficients of the equalizer using the first set of digital symbols and the second set of digital symbols.

2 . The PCIE receiver of claim 1 , wherein the training sequence is an analog training sequence processed by the ADC, and wherein the plurality of unscrambled portions is interleaved equally with the plurality of scrambled portions.

3 . The PCIE receiver of claim 1 , comprising:

clock circuitry configured to perform operations comprising:

providing a first set of clock signals to the ADC to generate the first set of digital symbols; and

periodically providing a second set of clock signals to the ADC to generate the second set of digital symbols, the second set of clock signals having a lower frequency than the first set of clock signals.

4 . The PCIE receiver of claim 3 , wherein the second set of clock signals are provided during a single sampling cycle of the ADC.

5 . The PCIE receiver of claim 3 , wherein the clock circuitry divides a reference clock by a first value to generate the first set of clock signals and divides the reference clock by a second value greater than the first value to generate the second set of clock signals.

6 . The PCIE receiver of claim 5 , wherein the first value is eight and the second value is nine.

7 . The PCIE receiver of claim 3 , wherein the operations performed by the one or more processors comprise:

controlling the clock circuitry to provide the first set of clock signals to the ADC to generate a first portion of the first set of digital symbols during a first set of sampling cycles;

detecting a condition for operating the ADC at a different clock frequency for a single sampling cycle;

in response to detecting the condition, controlling the clock circuitry to provide the second set of clock signals to the ADC to generate the second set of digital symbols during the single sampling cycle.

8 . The PCIE receiver of claim 7 , wherein the operations for controlling the clock circuitry to provide the second set of clock signals to the ADC comprise:

detecting a transition in a pulse gate signal; and

causing the clock circuitry to hold a value of one or more of the first set of clock signals for a specified time interval causing one or more pulses of the first set of clock signals to be swallowed.

9 . The PCIE receiver of claim 8 , comprising:

a NAND gate coupled to receive the one or more of the first set of clocks signals and the pulse gate signal.

10 . The PCIE receiver of claim 8 , wherein the plurality of unscrambled portions of the training sequence comprises a specified number of UIs and the plurality of unscrambled portions in the digital symbols comprises the specified number of UIs.

11 . The PCIE receiver of claim 7 , wherein the operations performed by the one or more processors comprise:

determining that the single sampling cycle has been completed by the ADC; and

in response to determining that the single sampling cycle has been completed by the ADC, controlling the clock circuitry to provide the first set of clock signals to the ADC to generate a second portion of the first set of digital symbols during one or more sampling cycles subsequent to the single sampling cycle.

12 . The PCIE receiver of claim 7 , wherein the operations performed by the one or more processors comprise:

accessing a configuration register associated with generating the condition; and

generating the condition based on the configuration register.

13 . The PCIE receiver of claim 12 , wherein the configuration register stores an individual value associated with generating the condition periodically, wherein the clock circuitry is controlled to provide the second set of clock signals at periodic intervals associated with the individual value.

14 . The PCIE receiver of claim 13 , wherein the periodic intervals are randomly adjusted over time.

15 . The PCIE receiver of claim 12 , wherein the configuration register stores an individual value associated with generating the condition one time, wherein the clock circuitry is controlled to provide the second set of clock signals at the one time.

16 . The PCIE receiver of claim 1 , wherein each time the ADC slips sampling the training sequence, the plurality of unscrambled portions in digital symbols representing the training sequence are rotated by a specified number of unit intervals (UIs) across different taps of the equalizer.

17 . The PCIE receiver of claim 16 , wherein the specified number of UIs comprises a quantity of UIs included in the plurality of unscrambled portions of the training sequence.

18 . A method comprising:

accessing a training sequence comprising a plurality of unscrambled portions interleaved with a plurality of scrambled portions;

instructing an analog-to-digital converter (ADC) to sample the training sequence to generate a first set of digital symbols representing the plurality of unscrambled portions and the plurality of scrambled portions to an equalizer;

causing the ADC to periodically slip sampling of the training sequence to generate a second set of digital symbols in which the plurality of unscrambled portions of the training sequence are randomized; and

training one or more coefficients of the equalizer using the first set of digital symbols and the second set of digital symbols.

19 . The method of claim 18 , wherein the training sequence is an analog training sequence processed by the ADC, and wherein the plurality of unscrambled portions are interleaved equally with the plurality of scrambled portions.

20 . A non-transitory computer-readable medium comprising computer-readable instructions that, when executed by one or more processors, cause the one or more processors to perform operations comprising:

accessing a training sequence comprising a plurality of unscrambled portions interleaved with a plurality of scrambled portions;

instructing an analog-to-digital converter (ADC) to sample the training sequence to generate a first set of digital symbols representing the plurality of unscrambled portions and the plurality of scrambled portions to an equalizer;

causing the ADC to periodically slip sampling of the training sequence to generate a second set of digital symbols in which the plurality of unscrambled portions of the training sequence are randomized; and

training one or more coefficients of the equalizer using the first set of digital symbols and the second set of digital symbols.