Granted Patent B2

US 12,626,664 · App. 18/951,596 · Granted May 12, 2026

Inventors: Chuanzhi Xu (Kunshan, CN); Yanqin Song (Kunshan, CN); Yong Wu (Kunshan, CN); Siming Hu (Kunshan, CN)

Assignee: Suzhou Govisionox Innovation Technology Co., Ltd.

G09G3/3241G09G3/3233H10K59/12H10K59/121H10K59/131G09G2300/0426G09G2300/0819G09G2300/0842G09G2300/0861G09G2320/045H10K59/126

Abstract

Claims (84)

1 . An array substrate, comprising:

a plurality of repeating units arranged in an array, wherein each repeating unit of the plurality of repeating units comprises two pixel circuits disposed in two adjacent columns, and each pixel circuit of the two pixel circuits comprises a plurality of function circuits; and

a plurality of first signal lines extending in a column direction;

wherein the plurality of function circuits in the each pixel circuit at least comprise a first initialization circuit or a second initialization circuit; in the each repeating unit, first initialization circuits in the two pixel circuits are connected to a same first signal line, or second initialization circuits in the two pixel circuits are connected to a same first signal line;

wherein the array substrate further comprises a plurality of data lines extending in the column direction, and pixel circuits of each column are connected to a respective data line of the plurality of data lines;

wherein the plurality of data lines and the plurality of first signal lines are disposed in a same layer;

wherein the array substrate comprises an active layer, a first conductive layer, and a second conductive layer, and the plurality of data lines and the plurality of first signal lines are disposed in the second conductive layer;

wherein two data lines are disposed between every two adjacent columns of repeating units; and the two data lines are disposed between every two adjacent first signal lines;

wherein the array substrate further comprises at least one shielding structure disposed between the two adjacent columns of repeating units, wherein in a thickness direction of the array substrate, a projection of the two data lines between the two adjacent columns of repeating units overlaps a projection of the at least one shielding structure between the two adjacent columns of repeating units; and

wherein the shielding structure is disposed in the active layer or the first conductive layer.

2 . The array substrate according to claim 1 , wherein each of the plurality of first signal lines is disposed between two pixel circuits of a respective one of the plurality of repeating units;

the plurality of function circuits in the each pixel circuit at least comprise a first initialization circuit and a second initialization circuit.

3 . The array substrate according to claim 2 , wherein

the array substrate further comprises a plurality of first via holes, the plurality of function circuits in the each repeating unit are connected to a first signal line through a respective one of plurality of first via holes; and

the first via hole corresponding to the plurality of function circuits in the each repeating unit is disposed between the two pixel circuits of the each repeating unit;

in the each repeating unit, first initialization circuits in the two pixel circuits are connected to the first signal line through one first via hole, and second initialization circuits in the two pixel circuits are connected to the respective first signal line through another one first via hole; and

for repeating units in two adjacent rows and a same column, a first initialization circuit in a pixel circuit in an i-th row and a j-th column and a second initialization circuit in a pixel circuit in an (i+1)-th row and the j-th column are connected to the respective first signal line through a same first via hole; the first initialization circuit and a second initialization circuit in the pixel circuit in the i-th row and the j-th column are connected to the first signal line through different first via holes, wherein i is a positive integer greater than or equal to 1, and j is a positive integer greater than or equal to 1.

4 . The array substrate according to claim 3 , wherein the each pixel circuit comprises a drive circuit, the first initialization circuit is used for initializing a first electrode of a light-emitting element, and the second initialization circuit is used for initializing the drive circuit; and

both the first initialization circuit and the second initialization circuit comprise a transistor, the transistor comprises a channel, and a channel of the first initialization circuit in the pixel circuit in the i-th row and the j-th column is disposed on a side of a channel of the second initialization circuit in the pixel circuit in the (i+1)-th row and the j-th column closest to the first signal line.

5 . The array substrate according to claim 1 , wherein the plurality of function circuits in the each pixel circuit at least comprise a first initialization circuit and a second initialization circuit, each of the first initialization circuit and the second initialization circuit comprises a transistor, the transistor comprises a channel, and for repeating units in two adjacent rows and a same column, a channel of a first initialization circuit in a repeating unit in a first row and a channel of a second initialization circuit in a repeating unit in a second row are arranged in a row direction; and

the array substrate comprises a plurality of scanning signal lines extending in the row direction, and the plurality of scanning signal lines and the plurality of first signal lines are disposed in different conductive layers; the channel of the first initialization circuit in the repeating unit in the first row and the channel of the second initialization circuit in the repeating unit in the second row overlap a same scanning signal line.

6 . The array substrate according to claim 1 , wherein the two pixel circuits in the each repeating unit are mirror-symmetric; each of the plurality of first signal lines is disposed on a center line of the two pixel circuits of the respective repeating unit.

7 . The array substrate according to claim 3 ,

wherein the each repeating unit is provided with two first conductive structures and a second conductive structure disposed between the two pixel circuits of the each repeating unit, and the second conductive structure is connected to the first signal line through the first via hole;

one of the two first conductive structures is connected to:

the first initialization circuit in the pixel circuit in the i-th row and the j-th column, and

the second initialization circuit in the pixel circuit in the (i+1)-th row and the j-th column, and

the second conductive structure;

the other one of the two first conductive structures is connected to:

a first initialization circuit in a pixel circuit in the i-th row and a (j+1)-th column, and

a second initialization circuit in a pixel circuit in the (i+1)-th row and the (j+1)-th column, and

the second conductive structure;

the first conductive structure connected to the first initialization circuit does not overlap a conductive signal line; and

the conductive signal line comprises the first signal line, a data line and a power signal line.

8 . The array substrate according to claim 7 , wherein the first conductive structures extend in a row direction; and

the array substrate comprises an active layer, a first conductive layer and a second conductive layer, and the first conductive structures and the second conductive structure are disposed in the active layer.

9 . The array substrate according to claim 1 , wherein the array substrate further comprises a plurality of power signal lines extending in the column direction and at least one second via hole, each power signal line of the plurality of power signal lines is used for supplying a power signal to a respective column of pixel circuits, the power signal lines and the shielding structure are disposed in different layers, and the shielding structure is connected to one of the plurality of power signal lines through the second via hole.

10 . The array substrate according to claim 9 , further comprising at least one coupling suppression structure extending in the column direction and disposed between two adjacent columns of repeating units; the coupling suppression structure and the plurality of data lines are disposed in different layers, and in a plan view the coupling suppression structure is located between the two data lines disposed between the two adjacent columns of repeating units;

the coupling suppression structure is disposed in the active layer or the first conductive layer; and

the coupling suppression structure is integrated with the shielding structure.

11 . The array substrate according to claim 1 , wherein the array substrate further comprises a plurality of power signal lines extending in the column direction, pixel circuits of each column are connected to a respective one of the plurality of power signal lines, and each of the plurality of power signal lines is used for supplying a power signal to the pixel circuits;

the plurality of power signal lines and the plurality of first signal lines are disposed in a same layer.

12 . The array substrate according to claim 11 , wherein the array substrate further comprises a plurality of power bonding lines disposed in the first conductive layer, and two adjacent power signal lines of the plurality of power signal lines are connected to each other through the power bonding line.

13 . The array substrate according to claim 11 , wherein each of the plurality of first signal lines is disposed between two adjacent power signal lines of the plurality of power signal lines; and

the two data lines between two adjacent columns of repeating units are disposed between two adjacent power signal lines of the plurality of power signal lines.

14 . The array substrate according to claim 11 , wherein each of the two pixel circuits comprises a drive circuit, a first initialization circuit, a second initialization circuit, a threshold compensation circuit, a data write circuit, a first light emission control circuit, a second light emission control circuit, and a storage capacitor;

wherein a control terminal of the drive circuit is connected to a first terminal of the storage capacitor, a first terminal of the drive circuit is connected to a second terminal of the first light emission control circuit, and a second terminal of the drive circuit is connected to a first terminal of the threshold compensation circuit;

wherein a first terminal of the data write circuit is connected to a corresponding data line, a second terminal of the data write circuit is connected to the first terminal of the drive circuit, and a control terminal of the data write circuit is connected to a second scanning signal line;

wherein a second terminal of the threshold compensation circuit is connected to the control terminal of the drive circuit, and a control terminal of the threshold compensation circuit is connected to the second scanning signal line;

wherein a first terminal of the second initialization circuit is connected to a corresponding first signal line, or a first terminal of the first initialization circuit is connected to the first signal line;

wherein a second terminal of the second initialization circuit is connected to the control terminal of the drive circuit;

wherein a control terminal of the second initialization circuit is connected to a first scanning signal line;

wherein a second terminal of the first initialization circuit is connected to an anode of a light-emitting element;

wherein a first terminal of the first light emission control circuit is connected to the power signal line, and a control terminal of the first light emission control circuit is connected to an enable signal line;

wherein a first terminal of the second light emission control circuit is connected to the second terminal of the drive circuit, a second terminal of the second light emission control circuit is connected to the anode of the light-emitting element, and a control terminal of the second light emission control circuit is connected to the enable signal line; and

wherein a second terminal of the storage capacitor is connected to the power signal line.

15 . The array substrate according to claim 1 , wherein the plurality of function circuits in each pixel circuit at least comprise a first initialization circuit and a second initialization circuit;

wherein in the each repeating unit, first initialization circuits in the two pixel circuits and second initialization circuits in the two pixel circuits are connected to a same first signal line among the plurality of first signal lines, and

wherein the first initialization circuits and the second initialization circuits in the repeating units of each column among the plurality of repeating units are connected to a same first signal line among the plurality of first signal lines.

16 . The array substrate according to claim 1 , wherein in a non-display area, each first signal line is connected to a driver chip through a corresponding lead,

in a display area, any two first signal lines are not connected to each other through a lead extending in a row direction.

17 . An array substrate, comprising:

a plurality of repeating units arranged in an array, wherein each repeating unit of the plurality of repeating units comprises two pixel circuits disposed in two adjacent columns, and each pixel circuit of the two pixel circuits comprises a plurality of function circuits; and

a plurality of first signal lines extending in a column direction,

wherein the plurality of function circuits in each pixel circuit at least comprise a drive circuit, a first initialization circuit for initializing a first electrode of a light-emitting element, and a second initialization circuit for initializing the drive circuit;

wherein in each repeating unit of the plurality of repeating units, first initialization circuits in the two pixel circuits and second initialization circuits in the two pixel circuits are connected to a same first signal line among the plurality of first signal lines;

wherein the first initialization circuits and the second initialization circuits in the repeating units of each column among the plurality of repeating units are connected to a same first signal line among the plurality of first signal lines;

wherein the array substrate further comprises a plurality of data lines extending in the column direction, and pixel circuits of each column are connected to a respective one of the plurality of data lines;

wherein the plurality of data lines and the plurality of first signal lines are disposed in a same layer;

wherein the array substrate comprises an active layer, a first conductive layer, and a second conductive layer, and the plurality of data lines and the plurality of first signal lines are disposed in the second conductive layer;

wherein two data lines are disposed between every two adjacent columns of repeating units; and the two data lines are disposed between every two adjacent first signal lines;

wherein the array substrate further comprises a plurality of power signal lines extending in the column direction, and pixel circuits of each column are connected to a respective one of the plurality of power signal lines, and each of the plurality of power signal lines is used for supplying a power signal to the pixel circuits; and

wherein the plurality of power signal lines and the plurality of first signal lines are disposed in the same layer;

wherein each of the plurality of first signal lines is disposed between two adjacent power signal lines among the plurality of power signal lines;

wherein the two data lines between two adjacent columns of repeating units are disposed between two adjacent power signal lines among the plurality of power signal lines; and

wherein each of the plurality of first signal lines is disposed between two pixel circuits of a respective one of the plurality of repeating units.

18 . An array substrate, comprising:

a plurality of repeating units arranged in an array, wherein each repeating unit of the plurality of repeating units comprises two pixel circuits disposed in two adjacent columns, and each pixel circuit of the two pixel circuits comprises a plurality of function circuits; and

a plurality of first signal lines extending in a column direction, wherein the plurality of function circuits in repeating units of each column are connected to a respective first signal line of the plurality of first signal lines, and the plurality of function circuits in the each repeating unit are connected to a same first signal line;

wherein each of the plurality of first signal lines is disposed between two pixel circuits of a respective one of the plurality of repeating units;

wherein the array substrate further comprises a plurality of first via holes, the plurality of function circuits in the each repeating unit are connected to a first signal line through a respective one of plurality of first via holes; and the first via hole corresponding to the plurality of function circuits in the each repeating unit is disposed between the two pixel circuits of the each repeating unit;

wherein the plurality of function circuits in each pixel circuit at least comprise a first initialization circuit and a second initialization circuit; and

wherein in the each repeating unit, first initialization circuits in the two pixel circuits are connected to the first signal line through one first via hole, and second initialization circuits in the two pixel circuits are connected to the respective first signal line through another one first via hole; and

for repeating units in two adjacent rows and a same column, a first initialization circuit in a pixel circuit in an i-th row and a j-th column and a second initialization circuit in a pixel circuit in an (i+1)-th row and the j-th column are connected to the respective first signal line through a same first via hole; the first initialization circuit and a second initialization circuit in the pixel circuit in the i-th row and the j-th column are connected to the first signal line through different first via holes, wherein i is a positive integer greater than or equal to 1, and j is a positive integer greater than or equal to 1.

Assignments (3)

Priority Claims (1)

Continuity (1)

References Cited (22)