IP Library Granted Patent US 12,650,908
Granted Patent B1
US 12,650,908 · App. 18/957,106 · Granted Jun 9, 2026

Parallel fault injection based on functional independence

Inventors: Joerg Mueller (Otterfing, DE); Christopher William Komar (Phoenix, AZ); Yogesh K. Goel (Fremont, CA)
Assignee: Cadence Design Systems, Inc.
G06F11/261G06F30/3308G06F30/33
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Quick Facts
Patent No.
US 12,650,908
App. No.
18/957,106
Granted
Jun 9, 2026
Kind
B1
Abstract

Various example embodiments provide for injecting multiple faults in parallel into a circuit design during fault simulation of the circuit design based on functional independence of the faults, where the fault injection and simulation may be performed as part of an electronic design automation (EDA) software system. According to various example embodiments, a structural analysis of a circuit design is performed to determine fault observability per strobe and the results of the analysis are used to determine independent fault groups for parallel injection during fault simulation of the circuit design.

Claims (61)

1 . A system comprising:

a memory storing instructions; and

a hardware processor communicatively coupled to the memory and configured by the instructions to perform operations comprising:

accessing fault set data describing a set of faults to be analyzed for a circuit design;

accessing strobe data describing a set of strobes for observing the circuit design;

performing a structural analysis of the circuit design to determine, for the set of faults, fault observability per strobe of the set of strobes;

determining, based on a result of the structural analysis, a set of independent fault groups from the set of faults, all faults within each individual independent fault group of the set of independent fault groups being injectable in parallel while each individual fault of the individual independent fault group remains independently observable by a subset of strobes of the set of strobes associated with the individual fault; and

performing one or more fault simulation runs serially on the circuit design based on the set of independent fault groups.

2 . The system of claim 1 , wherein the result of the structural analysis comprises a mapping of each single fault of the set of faults to a single subset of strobes of the set of strobes.

3 . The system of claim 1 , wherein the performing of the one or more fault simulation runs serially on the circuit design based on the set of independent fault groups comprises:

performing a single fault simulation run on the circuit design for a single independent fault group of the set of independent fault groups, the single fault simulation run comprising:

performing a fault simulation on the circuit design;

injecting in parallel all faults from the single independent fault group while performing the fault simulation on the circuit design; and

while injecting all faults from the single independent fault group, detecting for one or more events at a single subset of strobes of the set of strobes, the single subset of strobes being associated with the single independent fault group.

4 . The system of claim 3 , wherein the operations comprise:

after the single fault simulation is performed on the circuit design, performing a next fault simulation run on the circuit design for a next independent fault group of the set of independent fault groups.

5 . The system of claim 3 , wherein the performing of the one or more fault simulation runs serially on the circuit design based on the set of independent fault groups generates fault simulation results, and wherein the operations comprise:

extracting a set of fault annotations from the fault simulation results, the set of fault annotations describing whether one or more faults of the set of faults are observed at one or more strobes of the set of strobes during the one or more fault simulation runs.

6 . The system of claim 3 , wherein the performing of the one or more fault simulation runs serially on the circuit design based on the set of independent fault groups generates fault simulation results, and wherein the operations comprise:

extracting, from the fault simulation results, a set of fault annotations for the single independent fault group, the set of fault annotations describing whether one or more faults from the single independent fault group are observed at one or more strobes of the single subset of strobes during the single fault simulation run.

7 . The system of claim 6 , wherein the operations comprise:

receiving, from a user, at least one modification to the circuit design based on at least one fault annotation of the set of fault annotations.

8 . The system of claim 1 , wherein the performing of the one or more fault simulation runs serially on the circuit design based on the set of independent fault groups comprises:

performing a select fault simulation run on the circuit design for each select independent fault group of the set of independent fault groups serially, the select fault simulation run comprising:

performing a fault simulation on the circuit design;

injecting in parallel all faults from the select independent fault group while performing the fault simulation on the circuit design; and

while injecting all faults from the select independent fault group, detecting for one or more events at a select subset of strobes of the set of strobes, the select subset of strobes being associated with the select independent fault group.

9 . The system of claim 1 , wherein a given simulation run for a given independent fault group is configured to terminate only after each select fault of the given independent fault group is observed at at least one strobe of an associated subset of strobes of the set of strobes associated with the select fault.

10 . The system of claim 1 , wherein the structural analysis comprises at least one of a cone-of-influence (COI) analysis, an activatability analysis, or a propagatability analysis.

11 . A non-transitory computer-readable medium comprising instructions that, when executed by a hardware processor of a device, cause the device to perform operations comprising:

accessing fault set data describing a set of faults to be analyzed for a circuit design;

accessing strobe data describing a set of strobes for observing the circuit design;

performing a structural analysis of the circuit design to determine, for the set of faults, fault observability per strobe of the set of strobes;

determining, based on a result of the structural analysis, a set of independent fault groups from the set of faults, all faults within each individual independent fault group of the set of independent fault groups being injectable in parallel while each individual fault of the individual independent fault group remains independently observable by a subset of strobes of the set of strobes associated with the individual fault; and

performing one or more fault simulation runs serially on the circuit design based on the set of independent fault groups.

12 . The non-transitory computer-readable medium of claim 11 , wherein the result of the structural analysis comprises a mapping of each single fault of the set of faults to a single subset of strobes of the set of strobes.

13 . The non-transitory computer-readable medium of claim 11 , wherein the performing of the one or more fault simulation runs serially on the circuit design based on the set of independent fault groups comprises:

performing a single fault simulation run on the circuit design for a single independent fault group of the set of independent fault groups, the single fault simulation run comprising:

performing a fault simulation on the circuit design;

injecting in parallel all faults from the single independent fault group while performing the fault simulation on the circuit design; and

while injecting all faults from the single independent fault group, detecting for one or more faults at a single subset of strobes of the set of strobes, the single subset of strobes being associated with the single independent fault group.

14 . The non-transitory computer-readable medium of claim 13 , wherein the operations comprise:

after the single fault simulation is performed on the circuit design, performing a next fault simulation run on the circuit design for a next independent fault group of the set of independent fault groups.

15 . The non-transitory computer-readable medium of claim 13 , wherein the performing of the one or more fault simulation runs serially on the circuit design based on the set of independent fault groups generates fault simulation results, and wherein the operations comprise:

extracting a set of fault annotations from the fault simulation results, the set of fault annotations describing whether one or more faults of the set of faults are observed at one or more strobes of the set of strobes during the one or more fault simulation runs.

16 . The non-transitory computer-readable medium of claim 13 , wherein the performing of the one or more fault simulation runs serially on the circuit design based on the set of independent fault groups generates fault simulation results, and wherein the operations comprise:

extracting, from the fault simulation results, a set of fault annotations for the single independent fault group, the set of fault annotations describing whether one or more faults from the single independent fault group are observed at one or more strobes of the single subset of strobes during the single fault simulation run.

17 . The non-transitory computer-readable medium of claim 16 , wherein the operations comprise:

receiving, from a user, at least one modification to the circuit design based on at least one fault annotation of the set of fault annotations.

18 . The non-transitory computer-readable medium of claim 11 , wherein the performing of the one or more fault simulation runs serially on the circuit design based on the set of independent fault groups comprises:

performing a select fault simulation run on the circuit design for each select independent fault group of the set of independent fault groups serially, the select fault simulation run comprising:

performing a fault simulation on the circuit design;

injecting in parallel all faults from the select independent fault group while performing the fault simulation on the circuit design; and

while injecting all faults from the select independent fault group, detecting for one or more events at a select subset of strobes of the set of strobes, the select subset of strobes being associated with the select independent fault group.

19 . The non-transitory computer-readable medium of claim 11 , a given simulation run for a given independent fault group is configured to terminate only after each select fault of the given independent fault group is observed at at least one strobe of an associated subset of strobes of the set of strobes associated with the select fault.

20 . A method comprising:

accessing, by a hardware processor, fault set data describing a set of faults to be analyzed for a circuit design;

accessing, by the hardware processor, strobe data describing a set of strobes for observing the circuit design;

performing, by the hardware processor, a structural analysis of the circuit design to determine, for the set of faults, fault observability per strobe of the set of strobes;

determining, by the hardware processor and based on a result of the structural analysis, a set of independent fault groups from the set of faults, all faults within each individual independent fault group of the set of independent fault groups being injectable in parallel while each individual fault of the individual independent fault group remains independently observable by a subset of strobes of the set of strobes associated with the individual fault; and

performing, by the hardware processor, one or more fault simulation runs serially on the circuit design based on the set of independent fault groups.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2025
From: MUELLER, JOERG; KOMAR, CHRISTOPHER WILLIAM; GOEL, YOGESH K.
To: CADENCE DESIGN SYSTEMS, INC.
Reel/Frame 071288/0940 →
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