METHOD AND TENSOR TRAVERSAL ENGINE FOR STRIDED MEMORY ACCESS DURING EXECUTION OF NEURAL NETWORKS

1 . A method for executing a data transfer operation from a source memory component to a destination memory component, the method comprising:

accessing a pointer array comprising a first pointer array element representing a first source data block in the source memory component, the first pointer array element comprising:

a first source address for the first source data block; and

a first source block length for the first source data block;

writing the first source address to a source address register as a current source address;

writing the first source block length to a source block counter as a current source block count;

transferring a first source data word stored at the current source address in the source address register to a current destination address in a destination address register;

incrementing the current source address in the source address register; and

decrementing the current source block count in the source block counter.

2 . The method of claim 1 , further comprising:

accessing a control signal in a control signal register, the control signal comprising an initial destination address;

writing the initial destination address to the destination address register as the current destination address; and

incrementing the current destination address in the destination address register.

3 . The method of claim 1 , further comprising:

accessing a control signal in a control signal register, the control signal comprising:

a base pointer array address; and

a pointer array length; and

loading the pointer array into a pointer array queue based on the base pointer address and the pointer array length.

4 . The method of claim 3 , further comprising:

reading the first source address from the first pointer array element in the pointer array queue;

reading the first source block length from the first pointer array element in the pointer array queue; and

dequeuing the first pointer array element from the pointer array queue.

5 . The method of claim 1 , further comprising:

writing a base pointer array address to a pointer address register as a current pointer array address; and

for each pointer array element in a set of pointer array elements in the pointer array:

reading a current pointer array address in the pointer address register;

reading a respective source address for a respective source data block from a respective pointer array element at the current pointer array address;

writing the respective source address to the source address register as the current source address;

reading a respective source block length for the respective source data block from the pointer array element at the current pointer array address;

writing the respective source block length for the source data block to the source block counter as the current source block count; and

incrementing the current pointer array address in the pointer address register.

6 . The method of claim 1 , wherein transferring the first source data word stored at the current source address in the source address register to the current destination address in a destination address register comprises:

loading the first source data word from the current source address into a transpose buffer according to a first buffer dimension of the transpose buffer; and

transferring the first source data word from the transpose buffer according to a second buffer dimension of the transpose buffer.

7 . The method of claim 1 , wherein transferring the first source data word stored at the current source address in the source address register to the current destination address in a destination address register comprises:

loading the first source data word from the current source address into a data buffer; and

transferring the first source data word from the data buffer to the current destination address.

8 . The method of claim 1 , further comprising:

accessing a control signal in a control signal register, the control signal:

representing a source access pattern in the source memory component, the source access pattern defining a first dimension; and

comprising a first source stride length in the first dimension; and

advancing the current source address in the source address register based on the first source stride length and the current source address.

9 . The method of claim 1 , further comprising:

accessing a control signal in a control signal register, the control signal:

representing a destination storage pattern in the destination memory component, the destination storage pattern defining a first dimension; and

comprising a first destination stride length in the first dimension; and

advancing the current destination address in the destination address register based on the first destination stride length and the current destination address.

10 . A method for executing a data transfer operation, the method comprising:

accessing a source pointer array comprising a first source pointer array element representing a first source data block in a source memory component, the first source pointer array element comprising:

a first source address for the first source data block; and

a first source block length for the first source data block;

writing the first source address to a source address register as a current source address;

writing the first source block length to a source block counter as a current source block count;

enqueuing a first source data word stored at a current source address in the source address register to a data buffer;

incrementing the current source address in the source address register; and

decrementing the current source block count in the source block counter.

11 . The method of claim 10 , further comprising:

accessing a destination pointer array comprising a first destination pointer array element representing a first destination block in a destination memory component, the first destination pointer array element comprising:

a first destination address for the first destination block; and

a first destination block length for the first destination data block;

writing the first destination address to a destination address register as a current destination address;

writing the first destination block length to a destination block counter as a current destination block count;

dequeuing the first source data word stored in the data buffer to the current destination address in the destination address register;

incrementing the current destination address in the destination address register; and

decrementing the destination block count in the destination block counter.

12 . The method of claim 11 :

further comprising accessing a control signal in a control signal register, the control signal:

representing a custom destination storage pattern comprising the first destination block; and

comprising a base destination pointer array address; and

wherein accessing a destination pointer array comprises accessing the destination pointer array at the base destination pointer array address.

13 . The method of claim 10 :

further comprising accessing a control signal in a control signal register, the control signal:

representing a custom source access pattern comprising the first source data block; and

comprising a base source pointer array address; and

wherein accessing a source pointer array comprises accessing the source pointer array at the base source pointer array address.

14 . A tensor traversal engine in a processor system comprising a source memory component and a destination memory component, the tensor traversal engine comprising:

a source pointer address register;

a source pointer array counter;

a data buffer; and

control logic configured to:

read a current source pointer array address in the source pointer address register;

read a source address for a source data block in the source memory component from a source pointer array element at the current source pointer array address;

transfer the source data block at the source address to the data buffer;

increment the current source pointer array address in the source pointer address register; and

decrement a current source pointer array count in the source pointer array counter.

15 . The tensor traversal engine of claim 14 :

further comprising a destination pointer address register;

further comprising a destination pointer array counter; and

wherein the control logic is further configured to:

read a current destination pointer array address in the destination pointer address register;

read a destination address for a destination block in the destination memory component from a destination pointer array element at the current destination pointer array address;

transfer the source data block in the data buffer to the destination address;

increment the current destination pointer array address in the destination pointer address register; and

decrement a current destination pointer array count in the destination pointer array counter.

16 . The tensor traversal engine of claim 15 :

further comprising a control signal register configured to store a control signal for a data transfer operation from the source memory component to the destination memory component, the control signal comprising:

a base destination pointer array address; and

a destination pointer array length; and

wherein the control logic is further configured to:

write the base destination pointer array address to the destination pointer address register; and

write the destination pointer array length to the destination pointer array counter.

17 . The tensor traversal engine of claim 14 :

further comprising a control signal register configured to store a control signal for a data transfer operation from the source memory component to the destination memory component, the control signal comprising:

a base source pointer array address; and

a source pointer array length; and

wherein the control logic is further configured to:

write the base source pointer array address to the source pointer address register; and

write the source pointer array length to the source pointer array counter.

18 . The tensor traversal engine of claim 14 , further comprising:

a control signal register configured to store a control signal for a strided data transfer operation from the source memory component to the destination memory component, the control signal comprising a destination stride count; and

a destination stride counter configured to store the destination stride count.

19 . The tensor traversal engine of claim 14 , further comprising:

a control signal register configured to store a control signal for a strided data transfer operation from the source memory component to the destination memory component, the control signal comprising a source stride count;

a source stride counter configured to store the source stride count.

20 . The tensor traversal engine of claim 14 , further comprising:

a control signal register configured to store a control signal for a data transfer operation from the source memory component to the destination memory component, the control signal comprising:

a source pointer array length; and

a destination pointer array length;

a source pointer array queue configured to store a set of source pointer array elements characterized by the source pointer array length; and

a destination pointer array queue configured to store a set of destination pointer array elements characterized by the destination pointer array length.