LIGHT-LOAD RECOVERY IN A MULTI-LEVEL CONVERTER
Circuits and methods that solve the light-load problem of a multi-level converter by generating a ripple signal in the control loop of the multi-level converter that causes a large output current ripple during light load conditions. This added current ripple does not change the average output current but does create a temporary positive and negative current that can be used to balance and charge/discharge the fly capacitors of the multi-level converter. An alternative approach is to add extra switching cycles for the fly capacitors when the output ripple current crosses zero.
1 . (canceled)
2 . A method of improving light load recovery in an M-level converter configured to transform an input voltage applied to an input terminal of the M-level converter to an output voltage on an output terminal of the M-level converter in response to input signals from a controller defining charging cycles and discharging cycles for the M-level converter, the method comprising:
adding an extra charging cycle near or at a zero-current crossing point after a discharging cycle; and
adding an extra discharging cycle near or at a zero-current crossing point after a charging cycle.
3 . The method of claim 2 , further comprising selectively injecting a sub-harmonic signal into a signal path of the controller.
4 . The method of claim 3 , wherein the sub-harmonic signal induces a sub-harmonic ripple at the output terminal of the M-level converter.
5 . The method of claim 3 , wherein the M-level converter comprises at least one fly capacitor, and wherein the sub-harmonic signal induces a sub-harmonic ripple at the output terminal of the M-level converter to facilitate balancing of charge across the at least one fly capacitor.
6 . The method of claim 3 , wherein the controller comprises a comparison device having an input coupled to the output terminal of the M-level converter, the method further comprising selectively injecting the sub-harmonic signal in the signal path between the output terminal and the comparison device.
7 . The method of claim 3 , wherein the controller comprises a comparison device having a reference signal input, the method further comprising selectively injecting the sub-harmonic signal at the reference signal input.
8 . The method of claim 3 , wherein the controller comprises a compensation circuit, the method further comprising selectively injecting the sub-harmonic signal in the signal path after the compensation circuit.
9 . The method of claim 3 , wherein the controller comprises a compensation circuit, the method further comprising selectively injecting the sub-harmonic signal in the signal path before the compensation circuit.
10 . The method of claim 3 , wherein the controller comprises a pulse-width modulation generator, the method further comprising selectively injecting the sub-harmonic signal in the signal path after the pulse-width modulation generator.
11 . The method of claim 3 , further comprising selectively injecting the sub-harmonic signal when an average current through the output terminal is approximately zero amps.
12 . The method of claim 3 , further comprising selectively injecting the sub-harmonic signal when a light load is present on the output terminal.
13 . The method of claim 3 , further comprising selectively injecting a scaled sub-harmonic signal as a function of the absolute value of an average current through the output terminal.
14 . The method of claim 3 , wherein the M-level converter has a switching frequency, and wherein the sub-harmonic signal has a frequency about one-half the switching frequency of the M-level converter.
15 . The method of claim 3 , wherein the M-level converter has a switching frequency, and wherein the sub-harmonic signal has a frequency less than one-half the switching frequency of the M-level converter.
16 . The method of claim 3 , wherein the sub-harmonic signal creates temporary positive and negative currents sufficient to enable charge balancing of at least one fly capacitor in the M-level converter.
17 . The method of claim 3 , wherein the sub-harmonic signal is an AC waveform.
18 . The method of claim 3 , wherein the sub-harmonic signal is an AC waveform having an average voltage of zero.
19 . The method of claim 3 , wherein injecting the sub-harmonic signal is by altering a timing of a digital waveform generated by the controller that controls operation of the M-level converter.
20 . The method of claim 3 , wherein injecting the sub-harmonic signal is by altering a timing of a pulse-width modulated signal.
21 . A multi-level converter comprising:
an M-level converter cell configured to transform an input voltage applied to an input terminal of the M-level converter cell to an output voltage on an output terminal of the M-level converter cell in response to control inputs; and
a controller coupled to the M-level converter cell, wherein the controller is configured to:
monitor a node of the M-level converter cell;
define charging cycles and discharging cycles for the M-level converter in response to monitoring the node;
generate the control inputs to the M-level converter cell as a function of the defined charging cycles and the defined discharging cycles;
add an extra charging cycle near or at a zero-current crossing point after a discharging cycle; and
add an extra discharging cycle near or at a zero-current crossing point after a charging cycle.
22 . The multi-level converter of claim 21 , further comprising a sub-harmonic signal generator coupled to the controller, wherein the sub-harmonic signal generator is configured to selectively inject a sub-harmonic signal into a signal path of the controller.
23 . The multi-level converter of claim 22 , wherein the sub-harmonic signal generator is configured to inject the sub-harmonic signal into the signal path of the controller to induce a sub-harmonic ripple at the output terminal of the M-level converter cell.
24 . The multi-level converter of claim 22 , wherein the M-level converter cell comprises at least one fly capacitor, and wherein the sub-harmonic signal generator is configured to inject the sub-harmonic signal into the signal path of the controller to induce a sub-harmonic ripple at the output terminal of the M-level converter cell to facilitate balancing of charge across the at least one fly capacitor.
25 . The multi-level converter of claim 22 , wherein the controller comprises a comparison device having an input coupled to the output terminal of the M-level converter cell, and wherein the sub-harmonic signal generator is configured to selectively inject the sub-harmonic signal in the signal path between the output terminal and the comparison device.
26 . The multi-level converter of claim 22 , wherein the controller comprises a comparison device having a reference signal input, and wherein the sub-harmonic signal generator is configured to selectively inject the sub-harmonic signal at the reference signal input.
27 . The multi-level converter of claim 22 , wherein the controller comprises a compensation circuit, and wherein the sub-harmonic signal generator is configured to selectively inject the sub-harmonic signal in the signal path after the compensation circuit.
28 . The multi-level converter of claim 22 , wherein the controller comprises a compensation circuit, and wherein the sub-harmonic signal generator is configured to selectively inject the sub-harmonic signal in the signal path before the compensation circuit.
29 . The multi-level converter of claim 22 , wherein the controller comprises a pulse-width modulation generator, and wherein the sub-harmonic signal generator is configured to selectively inject the sub-harmonic signal in the signal path after the pulse-width modulation generator.
30 . The multi-level converter of claim 22 , wherein the sub-harmonic signal generator is configured to inject the sub-harmonic signal when an average current through the output terminal is approximately zero amps.
31 . The multi-level converter of claim 22 , wherein the sub-harmonic signal generator is configured to inject the sub-harmonic signal when a light load is present on the output terminal.
32 . The multi-level converter of claim 22 , wherein the sub-harmonic signal generator is configured to inject a scaled sub-harmonic signal as a function of the absolute value of an average current through the output terminal.
33 . The multi-level converter of claim 22 , wherein the M-level converter cell has a switching frequency, and wherein the sub-harmonic signal has a frequency about one-half the switching frequency of the M-level converter cell.
34 . The multi-level converter of claim 22 , wherein the M-level converter cell has a switching frequency, and wherein the sub-harmonic signal has a frequency less than one-half the switching frequency of the M-level converter cell.
35 . The multi-level converter of claim 22 , wherein the sub-harmonic signal generator is configured to inject the sub-harmonic signal to create temporary positive and negative currents sufficient to enable charge balancing of at least one fly capacitor in the M-level converter cell.
36 . The multi-level converter of claim 22 , wherein the sub-harmonic signal is an AC waveform.
37 . The multi-level converter of claim 22 , wherein the sub-harmonic signal is an AC waveform having an average voltage of zero.
38 . The multi-level converter of claim 22 , wherein the sub-harmonic signal generator is configured to inject the sub-harmonic signal into the signal path of the controller by altering a timing of a digital waveform generated by the controller.
39 . The multi-level converter of claim 22 , wherein the control inputs comprise a pulse-width modulated signal, and wherein the sub-harmonic signal generator is configured to inject the sub-harmonic signal into the signal path of the controller by altering a timing of the pulse-width modulated signal.
40 . A multi-level converter comprising:
an M-level converter cell configured to transform an input voltage applied to an input terminal to an output voltage on an output terminal in response to control inputs;
a controller coupled to the M-level converter cell, wherein the controller is configured to:
monitor a node of the M-level converter cell; and
generate the control inputs to the M-level converter cell in response to monitoring the node; and
a sub-harmonic signal generator coupled to the controller, wherein the sub-harmonic signal generator is configured to selectively inject a sub-harmonic signal into a signal path of the controller.
41 . The multi-level converter of claim 40 , wherein the sub-harmonic signal generator is configured to inject the sub-harmonic signal when an average current through the output terminal is approximately zero amps.
42 . The multi-level converter of claim 40 , wherein the sub-harmonic signal generator is configured to inject the sub-harmonic signal by:
scaling a degree of injection of the sub-harmonic signal as a function of the absolute value of an average current through the output terminal to obtain a scaled sub-harmonic signal; and
injecting the scaled sub-harmonic signal into the signal path of the controller.
43 . The multi-level converter of claim 42 , wherein the scaling comprises scaling an amplitude of the sub-harmonic signal and/or altering a duty cycle of injection of the sub-harmonic signal to obtain the scaled sub-harmonic signal.
44 . The multi-level converter of claim 40 , wherein the output terminal is configured to be coupled to an inductor.