MULTICORE SHARED CACHE OPERATION ENGINE
Techniques including receiving configuration information for a trigger control channel of the one or more trigger control channels, the configuration information defining a first one or more triggering events, receiving a first memory management command, store the first memory management command, detecting a first one or more triggering events, and triggering the stored first memory management command based on the detected first one or more triggering events.
1 . A system comprising:
an interface; and
a controller coupled to the interface and configurable to:
receive a first memory command via the interface to perform a first memory operation;
receive a first event from the interface; and
output the first memory command to perform the first memory operation in response the first event.
2 . The system of claim 1 , further comprising a system bus coupled to the interface.
3 . The system of claim 2 , wherein the system bus includes a packet streaming interface link bus.
4 . The system of claim 1 , further comprising an arbitrator coupled to the controller and configured to arbitrate among memory commands.
5 . The system of claim 1 , further comprising a memory mapped register coupled to the controller and configured to receive a second memory command to perform a second memory operation.
6 . The system of claim 5 , wherein the controller is configurable to:
receive a second event from the interface;
output the second memory command to perform the second memory operation in response the second event.
7 . The system of claim 5 , further comprising a local bus coupled to the controller, wherein the controller is configurable to:
detect a second event on the local bus; and
output the second memory command to perform the second memory operation in response the second event.
8 . The system of claim 1 , further comprising a configuration register coupled to the controller and configured to store an indication of the interface used to obtain the first memory command.
9 . The system of claim 1 , further comprising a configuration register coupled to the controller and configured to store an indication of a queue to that the first memory command should be sent to.
10 . The system of claim 1 , further comprising a bus coupled to the controller, wherein the controller is configurable to output a second event on the bus after the first memory command is triggered.
11 . The system of claim 10 , further comprising a configuration register coupled to the controller and configured to store an indication of the second event to output on the bus after the first memory command is triggered.
12 . The system of claim 1 , wherein the first memory command is a transfer command to move data from a source location to a destination location.
13 . A system comprising:
a system bus; and
a memory controller coupled to the system bus and including:
a local bus;
a buffer configured to store:
a first memory command to perform a first memory operation; and
a second memory command to perform a second memory operation,
wherein the memory controller is configurable to:
receive a first set of bits from the system bus;
detect a second set of bits on the local bus;
output the first memory command to perform the first memory operation in response to the first set of bits; and
output the second memory command to perform the second memory operation in response to the second set of bits.
14 . The system of claim 13 , wherein the buffer is configured to receive the first memory command from the system bus.
15 . The system of claim 13 ,
wherein the memory controller includes a memory mapped register coupled to the buffer, and
wherein the buffer is configured to receive the second memory command from the memory mapped register.
16 . The system of claim 15 , further comprising a processing core coupled to the memory mapped register and configurable to write the second memory command to the memory mapped register.
17 . The system of claim 13 ,
wherein the first memory command includes a virtual address, and
wherein the memory controller includes a memory management unit configured to translate the virtual address to a physical address.
18 . The system of claim 13 , further comprising:
a power management controller coupled to the system bus; and
a security controller coupled to the system bus.
19 . The system of claim 13 , wherein the first memory command is a transfer command to move data from a source location to a destination location.
20 . The system of claim 13 , wherein the memory controller includes an arbitrator configured to arbitrate between the first memory command and the second memory command.