Method And Apparatus For Use In Digitally Tuning A Capacitor In An Integrated Circuit Device
A method and apparatus for use in a digitally tuning a capacitor in an integrated circuit device is described. A Digitally Tuned Capacitor DTC is described which facilitates digitally controlling capacitance applied between a first and second terminal. In some embodiments, the first terminal comprises an RF+ terminal and the second terminal comprises an RF− terminal. In accordance with some embodiments, the DTCs comprise a plurality of sub-circuits ordered in significance from least significant bit (LSB) to most significant bit (MSB) sub-circuits, wherein the plurality of significant bit sub-circuits are coupled together in parallel, and wherein each sub-circuit has a first node coupled to the first RF terminal, and a second node coupled to the second RF terminal. The DTCs further include an input means for receiving a digital control word, wherein the digital control word comprises bits that are similarly ordered in significance from an LSB to an MSB.
1 . (canceled)
2 . A digitally tuned capacitor (DTC), comprising:
a plurality of sub-circuits coupled in parallel between a first radio frequency (RF) terminal and a second RF terminal, wherein each sub-circuit comprises:
a stack of switching field effect transistors (FETs) coupled in series;
a metal-insulator-metal (MIM) capacitor coupled in series with the stack of switching FETs;
a plurality of gate resistors, wherein each gate resistor is coupled to a gate of a corresponding switching FET; and
a plurality of drain-to-source resistors, wherein each drain-to-source resistor is coupled across a drain and source of a corresponding switching FET;
wherein
capacitance values of the sub-circuits are assigned based on a weighting scheme from a least significant bit (LSB) sub-circuit to a most significant bit (MSB) sub-circuit; and
gates of the switching FETs in each sub-circuit are configured to receive a corresponding bit of a digital control word to control switching operation of the sub-circuit.
3 . The DTC of claim 2 , wherein the MIM capacitor in each sub-circuit is coupled to the first RF terminal and the stack of switching FETs is coupled between the MIM capacitor and the second RF terminal.
4 . The DTC of claim 2 , wherein each next significant bit sub-circuit comprises twice the number of unit cells as its previous significant bit sub-circuit.
5 . The DTC of claim 2 , wherein the LSB sub-circuit comprises a unit cell having a single stack of switching FETs and a single MIM capacitor.
6 . The DTC of claim 2 , wherein the switching FETs are configured to receive a negative voltage to turn OFF and a positive voltage to turn ON.
7 . The DTC of claim 2 , wherein the stack of switching FETs is configured to provide power handling capability of at least 35 dBm.
8 . The DTC of claim 2 , wherein the gate resistors in each successive significant bit sub-circuit have resistance values that are scaled by one-half relative to their previous significant bit sub-circuit.
9 . The DTC of claim 2 , wherein the drain-to-source resistors in each successive significant bit sub-circuit have resistance values that are scaled by one-half relative to their previous significant bit sub-circuit.
10 . The DTC of claim 2 , wherein the switching FETs comprise silicon-on-insulator (SOI) MOSFETs.
11 . The DTC of claim 2 , wherein resistance of the plurality of gate resistors or the plurality of drain-to-source resistors are assigned according to a resistance weighting scheme that is inversely proportional to the weighting scheme of the capacitance values of the sub-circuits.
12 . The DTC of claim 2 , wherein each unit cell of the sub-circuits has identical Q-factor values when in an ON state.
13 . A digitally tuned capacitor (DTC), comprising:
a plurality of sub-circuits coupled in parallel between first and second RF terminals;
wherein each sub-circuit comprises a unit cell comprising:
a plurality of stacked switching field effect transistors (FETs) coupled in series;
a metal-insulator-metal (MIM) capacitor coupled in series with the stacked switching FETs;
a plurality of gate resistors each coupled to a gate of a corresponding switching FET and coupled together at a control node; and
wherein
each next significant bit sub-circuit comprises a greater number of unit cells coupled in parallel than its previous significant bit sub-circuit according to a selected weighting scheme, and
the control node of each sub-circuit is configured to receive a bit of a digital control word to control switching operation of the stacked switching FETs.
14 . The DTC of claim 13 , wherein each unit cell's Q-factor value is determined by an ON resistance of the stacked switching FETs and a capacitance of the MIM capacitor.
15 . The DTC of claim 13 , wherein the unit cells are weighted according to a thermometer coding scheme.
16 . The DTC of claim 13 , wherein an effective stack height of the stacked switching FETs is increased by voltage division between the MIM capacitor and the stacked switching FETs.
17 . The DTC of claim 13 , wherein the minimum capacitance of the DTC is based on selected sizes of FETs in the stacked switching FETs.
18 . The DTC of claim 13 , wherein each unit cell maintains a constant Q-factor value when all switching FETs in the unit cell are turned ON.
19 . The DTC of claim 13 , wherein the MIM capacitor is positioned at a top of the stacked switching FETs relative to the RF terminals.
20 . The DTC of claim 13 , wherein each switching FET comprises an accumulated charge sink (ACS) terminal coupled to its gate terminal via a diode.
21 . The DTC of claim 13 , wherein the DTC is configured to provide a linear capacitance response versus the digital control word.