IP Library Patent Application 18984053
Patent Application
App. No. 18/984,053

ENGINEERED SUBSTRATE STRUCTURES FOR POWER AND RF APPLICATIONS

Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US None
App. No.
18/984,053
Abstract

A method of manufacturing a substrate includes forming a support structure by providing a polycrystalline ceramic core, forming a first adhesion layer coupled to the polycrystalline ceramic core, forming a conductive layer coupled to the first adhesion layer, forming a second adhesion layer coupled to the conductive layer, and forming a barrier layer coupled to the second adhesion layer. The method also includes forming a bonding layer coupled to the support structure, joining a substantially single crystal layer to the bonding layer, wherein the substantially single crystal layer comprises at least one of silicon carbide, sapphire, or gallium nitride, and forming one or more epitaxial III-V layers coupled to the substantially single crystal layer.

Claims (32)

1 . A method of manufacturing a substrate, the method comprising:

forming a support structure by:

providing a polycrystalline ceramic core;

forming a first adhesion layer coupled to the polycrystalline ceramic core;

forming a conductive layer coupled to the first adhesion layer;

forming a second adhesion layer coupled to the conductive layer; and

forming a barrier layer coupled to the second adhesion layer;

forming a bonding layer coupled to the support structure;

joining a substantially single crystal layer to the bonding layer, wherein the substantially single crystal layer comprises at least one of silicon carbide, sapphire, or gallium nitride; and

forming one or more epitaxial semiconductor layers coupled to the substantially single crystal layer.

2 . The method of claim 1 , wherein:

the first adhesion layer encapsulates the polycrystalline ceramic core;

the conductive layer encapsulates the first adhesion layer;

the second adhesion layer encapsulates the conductive layer; and

the barrier layer encapsulates the second adhesion layer.

3 . The method of claim 2 , wherein the first adhesion layer fully encapsulates the polycrystalline ceramic core.

4 . The method of claim 2 , wherein the conductive layer fully encapsulates the first adhesion layer.

5 . The method of claim 2 , wherein the second adhesion layer fully encapsulates the conductive layer.

6 . The method of claim 2 , wherein the barrier layer fully encapsulates the second adhesion layer.

7 . The method of claim 1 , further comprising forming an epitaxial silicon layer on the substantially single crystal layer.

8 . The method of claim 1 , wherein the polycrystalline ceramic core comprises aluminum nitride.

9 . The method of claim 1 , wherein the one or more epitaxial semiconductor layers comprise one or more epitaxial III-V layers.

10 . The method of claim 9 , wherein the one or more epitaxial III-V layers comprises an epitaxial gallium nitride layer.

11 . The method of claim 10 , wherein the epitaxial gallium nitride layer has a thickness greater than 5 μm.

12 . The method of claim 9 , wherein the one or more epitaxial III-V layers further comprise an epitaxial aluminum nitride layer.

13 . The method of claim 9 , wherein the one or more epitaxial III-V layers further comprise an epitaxial aluminum gallium nitride layer.

14 . The method of claim 9 , wherein the one or more epitaxial III-V layers further comprise a combination of an epitaxial aluminum nitride layer and an epitaxial aluminum gallium nitride layer.

15 . The method of claim 1 , further comprising, before forming the one or more epitaxial semiconductor layers, forming an epitaxial silicon layer coupled to the substantially single crystal layer, wherein the one or more epitaxial semiconductor layers are coupled to the epitaxial silicon layer.

16 . The method of claim 15 , wherein the epitaxial silicon layer is strained.

17 . The method of claim 1 , further comprising forming a plurality of vias passing from the epitaxial semiconductor layers to the substantially single crystal layer.

18 . The method of claim 1 , wherein the polycrystalline ceramic core has a coefficient of thermal expansion equal to the coefficient of thermal expansion of at least one of the one or more epitaxial semiconductor layers.

19 . The method of claim 1 , wherein forming the first adhesion layer comprises performing a low pressure chemical vapor deposition (LPCVD) process.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2024
From: ODNOBLYUDOV, VLADIMIR; BASCERI, CEM; FARRENS, SHARI
To: QROMIS, INC.
Reel/Frame 069613/0107 →