Hierarchical storage device with host controlled subdivisions
This disclosure provides techniques hierarchical address virtualization within a memory controller and configurable block device allocation. By performing address translation only at select hierarchical levels, a memory controller can be designed to have predictable I/O latency, with brief or otherwise negligible logical-to-physical address translation time. In one embodiment, address transition may be implemented entirely with logical gates and look-up tables of a memory controller integrated circuit, without requiring processor cycles. The disclosed virtualization scheme also provides for flexibility in customizing the configuration of virtual storage devices, to present nearly any desired configuration to a host or client.
1 . A storage apparatus comprising:
a host having a storage manager and a host-side interface; and
at least one storage drive, including a first storage drive comprising:
flash memory;
circuitry to, for incoming data write requests, each of the incoming data write requests being accompanied by incoming address information:
derive, from the accompanying incoming address information, a first address portion, a second address portion, and a third address portion;
identify an addressed block device from the first address portion;
identify an addressed segment within the addressed block device from the second address portion, wherein the addressed segment corresponds to one or more erase units; and
using the third address portion, identify bit fields, wherein the circuitry is to identify from a first one of the bit fields an erase unit corresponding to the addressed segment, and is to identify a storage location within the identified erase unit dependent on a second one of the bit fields; and
program associated data into the identified erase unit at the identified storage location; and
circuitry to:
maintain metadata specific to the addressed segment;
compare the specific metadata to at least one threshold; and
responsive to detection that the specific metadata has satisfied the at least one threshold, transmit, to the storage manager, via the host-side interface, an identifier for the addressed segment; and
wherein, dependent on receipt of the identifier for the addressed segment, the storage manager is to issue, via the host-side interface, one or more maintenance requests targeting the addressed segment.
2 . The storage apparatus of claim 1 wherein the one or more maintenance requests are to cause the first storage drive to responsively copy data from the identified storage location in the flash memory to a second storage location in the flash memory.
3 . The storage apparatus of claim 1 wherein the specific metadata represents a time since data was programmed into the one or more erase units.
4 . The storage apparatus of claim 1 wherein the circuitry to derive comprises at least one drive processor and wherein the first storage drive comprises instructions stored on at least one physical storage medium, said instructions when executed, to control actions of the at least one drive processor, and wherein the first storage drive is also to transmit, to the storage manager, an indication of a need for maintenance in association with the identifier for the addressed segment.
5 . The storage apparatus of claim 1 wherein the first storage drive is to receive a query from the storage manager, sent via the host-side interface, and wherein the first storage drive is to transmit the identifier for the addressed segment to the storage manager, in a manner responsive to the query.
6 . The storage apparatus of claim 1 wherein the first storage drive comprises circuitry to:
receive the one or more maintenance requests; and
responsive to the one or more maintenance requests, perform an erasure one or more erase units corresponding to the addressed segment.
7 . The storage apparatus of claim 6 wherein:
the circuitry to maintain the specific metadata is to maintain metadata on a basis that is respective to the identified erase unit, the metadata respective to the identified erase unit representing a number of times that the identified erase unit has been erased.
8 . The storage apparatus of claim 1 wherein the flash memory has a number of segments, including the addressed segment, and wherein the first storage drive comprises circuitry to:
receive a query issued by the storage manager, via the host-side interface;
transmit, to the storage manager, information identifying each of the segments; and
for each respective one of the segments, at least one request issued by the storage manager is dependent on the information which was transmitted to the storage manager identifying the respective one of the segments.
9 . The storage apparatus of claim 1 wherein each of the one or more erase units corresponds to a physical erase unit of the flash memory, wherein the first storage drive comprises circuitry to detect a failure condition of one of the physical erase units and to responsively remap the addressed segment to a different physical erase unit.
10 . The storage apparatus of claim 1 wherein:
the specific metadata indicates an extent to which associated memory can continue to receive additional write data without being erased.
11 . The storage apparatus of claim 1 wherein the first storage drive further comprises circuitry to, for each of the incoming data write requests:
assign an address value corresponding to the identified storage location; and
transmit the address value to the storage manager, via the host side interface.
12 . The storage apparatus of claim 1 wherein:
the flash memory has a number of structures;
the first storage drive comprises circuitry to:
store information representing the number of the structures; and
transmit, to the storage manager, an indication of the number of structures;
the storage manager is to responsively issue at least one request, to the first storage drive, and via the host-side interface, which is dependent on the number of the structures; and
the first storage drive is to fulfill the responsively-issued at least one request by issuing one or more commands to the flash memory for which a quantum of flash memory selected by the one or more commands is dependent on the number of the structures.
13 . The storage apparatus of claim 12 wherein the number of the structures corresponds to an amount of the flash memory that is to be physically erased as a unit.
14 . The storage apparatus of claim 1 wherein the addressed segment corresponds to an integer number of physical erase units for which a failure condition has not been detected, and wherein the third address portion is effective to specify a location within a range of locations that correspond to the integer number of physical erase units.
15 . The storage apparatus of claim 1 wherein:
the flash memory is to have block devices, including the addressed block device; and
the first storage drive comprises circuitry to:
store an erase count respective to each of the block devices;
receive a query, issued by the storage manager via the host-side interface, wherein said query is specific to one of the block devices and, responsive to the query, transmit, to the storage manager, information dependent on the stored erase count for the specific one of the block devices.
16 . The storage apparatus of claim 1 wherein:
the flash memory comprises multiple planes;
the first storage drive is to, for each one of a set of the incoming data write requests having sequential addressing, identify a commonly addressed page; and
the programming is performed such that associated data corresponding to the incoming data write requests of the set is programmed concurrently into respective ones of the multiple planes, using the identified commonly addressed page.
17 . The storage apparatus of claim 1 wherein:
for one of the incoming data write requests, the first storage drive is to generate an address value corresponding to the identified storage location and is to transmit the address value to the storage manager;
the storage manager, via the host-side interface, is to issue one or more read requests in a manner including addressing which is dependent upon the transmitted address value; and
the storage drive comprises circuitry to fulfill execution of the one or more read requests using the addressing.
18 . The storage apparatus of claim 1 wherein the first storage drive comprises circuitry to receive a query from the storage manager, issued via the host-side interface, and to responsively transmit information, to the storage manager, indicating at least one of a number of dies of the flash memory or a number of channels of the flash memory.
19 . The storage apparatus of claim 1 wherein at least one of a number of dies or a number of channels associated with the addressed block device is programmable by a command received by the first storage drive from the storage manager, the command being issued via the host-side interface.
20 . The storage apparatus of claim 1 wherein:
the specific metadata comprises physical storage location release information;
the first storage drive comprises circuitry to:
receive a query from the storage manager, issued via the host-side interface; and
responsive to the query, transmit information, to the storage manager, representing the storage location release information, in association with the identifier for the addressed segment; and
at least one of the one or more maintenance requests is dependent on the information representing the storage location release information which was transmitted to the storage manager.
21 . The storage apparatus of claim 1 wherein the first storage drive comprises circuitry to receive a release request from the storage manager, issued via the host-side interface, which indicates one or more storage locations, and to responsively mark each indicated storage location as released.
22 . The storage apparatus of claim 1 wherein:
the specific metadata comprises hot/cold information;
the first storage drive comprises circuitry to:
receive a query from the storage manager, issued via the host-side interface; and
responsive to the query, transmit information, to the storage manager, representing the hot/cold information, in association with the identifier for the addressed segment; and
at least one of the one or more maintenance requests is dependent on the information representing the hot/cold information which was transmitted to the storage manager, and further, is operable to cause the first storage drive to responsively copy data from the identified storage location in the flash memory to a second storage location in the flash memory.
23 . The storage apparatus of claim 1 wherein the circuitry to identify the bitfields is to partition the third address portion into a first discrete set of bits and a second discrete set of bits, the first one of the bitfields corresponding to the first discrete set of bits and the second one of the bitfields corresponding to the second discrete set of bits.
24 . The storage apparatus of claim 1 wherein the circuitry to identify the bitfields is to process the third address portion using a modulo operation, to identify a quotient and a remainder, wherein the first one of the bitfields corresponds to a first one of the quotient or the remainder, wherein the second one of the bitfields corresponds to a second one of the quotient or the remainder, and wherein a divisor of the modulo operation is free to be a non-power-of-two integer.
25 . A storage apparatus comprising:
a host having a storage manager and a host-side interface; and
at least one storage drive, including a first storage drive comprising:
flash memory;
circuitry to, for incoming data write requests, each of the incoming data write requests being accompanied by incoming address information:
derive, from the accompanying incoming address information, a first address portion, a second address portion, and a third address portion;
identify an addressed block device from the first address portion;
identify an addressed segment within the addressed block device from the second address portion, wherein the addressed segment corresponds to one or more erase units; and
using the third address portion, identify bit fields, wherein the circuitry is to identify from a first one of the bit fields an erase unit corresponding to the addressed segment, and is to identify a storage location within the identified erase unit dependent on a second one of the bit fields; and
program associated data into the identified erase unit at the identified storage location; and
circuitry to:
maintain metadata specific to the addressed segment;
compare the specific metadata to at least one threshold; and
responsive to detection that the specific metadata has satisfied the at least one threshold, transmit, to the storage manager, via the host-side interface, an identifier for the addressed segment; and
wherein, dependent on receipt of the identifier for the addressed segment, the storage manager is to issue one or more maintenance requests, via the host-side interface, targeting the addressed segment;
wherein, responsive to the one or more requests targeting the addressed segment, the first storage drive is to control physical erasure of flash memory associated with the addressed segment; and
wherein the first storage drive comprises circuitry to maintain, for the respective ones of the one or more physical erase units, second metadata representing a number of times that flash memory corresponding the respective physical erase unit has been physically erased and is to update, in connection with execution of the one or more maintenance requests, the second metadata.
26 . The storage apparatus of claim 25 wherein the first storage drive comprises circuitry to selectively transmit to the storage manager, information which is dependent upon the second metadata.
27 . The storage apparatus of claim 25 wherein:
the flash memory comprises multiple planes; and
in connection with execution a specific one of the one or more maintenance requests, the first storage drive is to control physical erasure of flash memory in each of the multiple planes.
28 . The storage apparatus of claim 25 wherein the first storage drive further comprises circuitry to:
track additional metadata which indicates an extent to which memory comprising the one or more erase units can continue to receive additional write data without being erased;
for a given one of the incoming data write requests for which the accompanying incoming address information designates the addressed segment, update the additional metadata; and
provide information representing the updated, additional metadata to the storage manager.