PHASE LOCK LOOP (PLL) SYNCHRONIZATION
In an embodiment, an apparatus includes a first integrated circuit (IC) chip comprising a first phase lock loop (PLL) configured to generate a first output clock signal and a second IC chip comprising a second PLL configured to generate a second output clock signal. The first output clock signal and the second output clock signal are synchronized based on a reference time signal.
1 . An apparatus comprising:
a first integrated circuit (IC) chip comprising a first phase lock loop (PLL) configured to generate a first output clock signal; and
a second IC chip comprising a second PLL configured to generate a second output clock signal, wherein the first output clock signal and the second output clock signal are synchronized based on a reference time signal.
2 . The apparatus of claim 1 , wherein the reference time signal is generated at a first particular cycle of a reference clock signal, wherein synchronization of the first output clock signal and the second output clock signal is initiated during a second particular cycle of the reference clock signal, and wherein the first particular cycle of the reference clock signal is a different cycle than the second particular cycle of the reference clock signal.
3 . The apparatus of claim 1 , wherein the first PLL comprises a first sigma delta modulator (SDM) and the second PLL comprises a second SDM.
4 . The apparatus of claim 3 , wherein the first PLL comprises a particular sigma-delta sequence and the second PLL comprises the particular sigma-delta sequence.
5 . The apparatus of claim 4 , wherein synchronization of the first output clock signal and the second output clock signal comprises synchronizing a starting point of the particular sigma-delta sequence in the first PLL and the second PLL.
6 . The apparatus of claim 3 , wherein the first PLL further comprises a first feedback divider controlled by a first divider ratio associated with the first SDM.
7 . The apparatus of claim 1 , wherein one or more timing components of the first PLL are configured to generate a synchronization signal to trigger phase synchronization of the first PLL if the reference time signal equals a pre-set reference time signal count value and the first PLL is in a locked state.
8 . The apparatus of claim 1 , wherein each of the first PLL and the second PLL comprises one or both of an integer mode PLL or a fractional mode PLL.
9 . The apparatus of claim 1 , wherein the first PLL and the second PLL are reset based on a combination of an active state of a synchronization enable signal and an active state of a reference time signal, wherein an inactive state of the synchronization enable signal prevents the reference time signal from resetting the PLL.
10 . A method comprising:
generating, by a first PLL of a first IC chip, a first output clock signal; and
generating, by second PLL of a second IC chip, a second output clock signal, wherein the first output clock signal and the second output clock signal are synchronized based on a reference time signal.
11 . The method of claim 10 , wherein the reference time signal is generated at a first particular cycle of a reference clock signal, wherein synchronization of the first output clock signal and the second output clock signal is initiated during a second particular cycle of the reference clock signal, and wherein the first particular cycle of the reference clock signal is a different cycle than the second particular cycle of the reference clock signal.
12 . The method of claim 10 , wherein the first PLL comprises a first SDM and the second PLL comprises a second SDM.
13 . The method of claim 12 , wherein the first PLL comprises a particular sigma-delta sequence and the second PLL comprises the particular sigma-delta sequence.
14 . The method of claim 13 , wherein synchronization of the first output clock signal and the second output clock signal comprises synchronizing a starting point of the particular sigma-delta sequence in the first PLL and the second PLL.
15 . The method of claim 12 , wherein the first PLL further comprises a first feedback divider controlled by a first divider ratio associated with the first SDM.
16 . The method of claim 10 , wherein one or more timing components of the first PLL are configured to generate a synchronization signal to trigger phase synchronization of the first PLL if the reference time signal equals a pre-set reference time signal count value and the first PLL is in a locked state.
17 . The method of claim 10 , wherein each of the first PLL and the second PLL comprises one or both of an integer mode PLL or a fractional mode PLL.
18 . The method of claim 10 , wherein the first PLL and the second PLL are reset based on a combination of an active state of a synchronization enable signal and an active state of a reference time signal, wherein an inactive state of the synchronization enable signal prevents the reference time signal from resetting the first PLL or the second PLL.