Memory Arrays Comprising Vertically-Alternating Tiers Of Insulative Material And Memory Cells And Methods Of Forming A Memory Array Comprising Memory Cells Individually Comprising A Transistor And A Capacitor
A memory array comprises vertically-alternating tiers of insulative material and memory cells, with the memory cells individually comprising a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. A capacitor of the memory cell comprises first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. A horizontal longitudinally-elongated sense line is in individual of the memory-cell tiers. Individual of the second source/drain regions of individual of the transistors that are in the same memory-cell tier are electrically coupled to the horizontal longitudinally-elongated sense line in that individual tier of memory cells. A capacitor-electrode structure extends elevationally through the vertically-alternating tiers. Individual of the second electrodes of individual of the capacitors are electrically coupled to the elevationally-extending capacitor-electrode structure. An access-line pillar extends elevationally through the vertically-alternating tiers. The gate of individual of the transistors in different of the memory-cell tiers comprises a portion of the elevationally-extending access-line pillar. Other embodiments, including method, are disclosed.
1 . A memory array comprising vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:
a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region, at least a portion of the channel region being horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions; and
a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region, the second capacitor electrodes of multiple of the capacitors in the array being electrically coupled with one another;
an access-line pillar extending elevationally through the vertically-alternating tiers, individual ones of the gates of individual ones of the transistors in different ones of the memory-cell tiers comprising a respective portion of the elevationally-extending access-line pillar;
the individual transistors comprising a gate insulator that is laterally between the gate and the channel region, the gate insulator being laterally between and separating the gate and the first source/drain region from physically contacting one another, the gate insulator being laterally between and separating the gate and the second source/drain region from physically contacting one another; and
the first and second source/drain regions each have a vertical side that is directly against both of the channel region and the gate insulator, a greater quantity of each of the vertical sides of the first and second source/drain regions being directly against the gate insulator than is directly against the channel region.
2 . The array of claim 1 wherein the channel region comprises two channel-region segments on opposite sides of the gate in a straight-line horizontal cross-section.
3 . The array of claim 2 wherein the channel region completely encircles the gate in the straight-line horizontal cross-section.
4 . The array of claim 1 wherein the channel region is on only one side of the gate in a straight-line horizontal cross-section.
5 . The array of claim 1 comprising another access-line pillar extending elevationally through the vertically-alternating tiers, the another access-line pillar comprising another gate of the individual transistors in the different memory-cell tiers.
6 . The array of claim 1 wherein the access-line pillar extends vertically or within 10° of vertical.
7 . The array of claim 1 wherein all of the channel region is horizontally-oriented for horizontal current flow there-through.
8 . The array of claim 1 wherein the first electrode is directly electrically coupled to the first source/drain region.
9 . The array of claim 1 comprising a horizontal longitudinally-elongated sense line in individual ones of the memory-cell tiers, individual ones of the second source/drain regions of individual ones of the transistors that are in the same memory-cell tier being electrically coupled to the horizontal longitudinally-elongated sense line in that individual tier of memory cells.
10 . A memory array comprising vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:
a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region, at least a portion of the channel region being horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions; and
a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region, the second capacitor electrodes of multiple of the capacitors in the array being electrically coupled with one another;
an access-line pillar extending elevationally through the vertically-alternating tiers, individual ones of the gates of individual ones of the transistors in different ones the memory-cell tiers comprising a respective portion of the elevationally-extending access-line pillar;
the individual transistors comprising a gate insulator that is laterally between the gate and the channel region, the gate insulator being laterally between and separating the gate and the first source/drain region from physically contacting one another, the gate insulator being laterally between and separating the gate and the second source/drain region from physically contacting one another; and
the first and second source/drain regions each have a vertical side that is directly against both of the channel region and the gate insulator, a greater quantity of each of the vertical sides of the first and second source/drain regions being directly against the channel region than is directly against the gate insulator.
11 . The array of claim 10 comprising a horizontal longitudinally-elongated sense line in individual ones of the memory-cell tiers, individual ones of the second source/drain regions of individual ones of the transistors that are in the same memory-cell tier being electrically coupled to the horizontal longitudinally-elongated sense line in that individual tier of memory cells.
12 . The array of claim 10 wherein the channel region comprises two channel-region segments on opposite sides of the gate in a straight-line horizontal cross-section.
13 . The array of claim 12 wherein the channel region completely encircles the gate in the straight-line horizontal cross-section.
14 . The array of claim 10 wherein the channel region is on only one side of the gate in a straight-line horizontal cross-section.
15 . The array of claim 10 comprising another access-line pillar extending elevationally through the vertically-alternating tiers, the another access-line pillar comprising another gate of the individual transistors in the different memory-cell tiers.
16 . A memory array comprising vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising:
a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region, at least a portion of the channel region being horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions; and
a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region, the second capacitor electrodes of multiple of the capacitors in the array being electrically coupled with one another;
an access-line pillar extending elevationally through the vertically-alternating tiers, individual ones of the gates of individual ones of the transistors in different ones of the memory-cell tiers comprising a respective portion of the elevationally-extending access-line pillar; and
the portion of the elevationally-extending access-line pillar in the individual transistors being completely laterally circumferentially surrounded by a combination of the first source/drain region, the second source/drain region and the channel region; the portion having a first pair of laterally-opposite sides and a second pair of laterally-opposite sides, the channel region being on the laterally-opposite sides of only one of the first or the second pair and not on the laterally-opposite sides of the other of the first pair or the second pair, the first source/drain region and the second source/drain region collectively being on the laterally-opposite sides of only the other of the first or the second pair and not on the laterally-opposite sides of the one of the first pair or the second pair.
17 . The array of claim 16 wherein the first and second pairs are orthogonal relative one another.
18 . The array of claim 16 comprising a horizontal longitudinally-elongated sense line in individual ones of the memory-cell tiers, individual ones of the second source/drain regions of individual ones of the transistors that are in the same memory-cell tier being electrically coupled to the horizontal longitudinally-elongated sense line in that individual tier of memory cells.
19 . The array of claim 16 wherein the channel region comprises two channel-region segments on opposite sides of the gate in a straight-line horizontal cross-section.
20 . The array of claim 16 wherein the channel region is on only one side of the gate in a straight-line horizontal cross-section.