SEMICONDUCTOR PACKAGE AND RELATED METHODS
Implementations of semiconductor packages may include: a first substrate having a first dielectric layer coupled between a first metal layer and a second metal layer; a second substrate having a second dielectric layer coupled between a third metal layer and a fourth metal layer. A first die may be coupled with a first electrical spacer coupled in a space between and coupled with the first substrate and the second substrate and a second die may be coupled with a second electrical spacer coupled in a space between and coupled with the first substrate and the second substrate.
1 . A semiconductor package comprising:
a first patterned layer;
a second patterned layer;
a power die directly coupled to the second patterned layer and coupled between the first patterned layer and the second patterned layer;
an electrical spacer coupled directly to the second patterned layer and between the power die and the second patterned layer; and
one or more flexible electrical supports directly coupled to the first patterned layer and the second patterned layer.
2 . The semiconductor package of claim 1 , wherein each of the one or more flexible electrical supports are directly coupled to the first patterned layer and to the second patterned layer.
3 . The semiconductor package of claim 1 , wherein the semiconductor package is a power module.
4 . The semiconductor package of claim 1 , further comprising a second electrical spacer coupled between the first patterned layer and the second patterned layer, wherein the second electrical spacer is physically separate from the electrical spacer, wherein the electrical spacer is directly coupled to both the power die and the second patterned layer through a solder separate from the electrical spacer.
5 . The semiconductor package of claim 1 , wherein the one or more flexible electrical supports comprise one of a spring or a sponge-like structure.
6 . The semiconductor package of claim 1 , wherein the first patterned layer is comprised in a first substrate and the second patterned layer is comprised in a second substrate.
7 . The semiconductor package of claim 6 , wherein the first substrate is larger than the second substrate.
8 . A semiconductor package comprising:
a first patterned layer;
a second patterned layer;
a first power die directly coupled to the first patterned layer and coupled between the first patterned layer and the second patterned layer;
a second power die directly coupled to the second patterned layer and coupled between the first patterned layer and the second patterned layer;
an electrical spacer coupled directly to the second patterned layer and coupled between the first die and the second patterned layer; and
one or more flexible electrical supports directly coupled to the first patterned layer and the second patterned layer.
9 . The semiconductor package of claim 8 , wherein each of the one or more flexible electrical supports are directly coupled to the first patterned layer and to the second patterned layer.
10 . The semiconductor package of claim 8 , wherein the semiconductor package is a power module.
11 . The semiconductor package of claim 8 , wherein the electrical spacer is directly coupled to the second patterned layer through a solder separate from the electrical spacer, wherein the electrical spacer directly electrically couples the first power die to only the second patterned layer.
12 . The semiconductor package of claim 8 , wherein the first patterned layer is comprised in a first substrate and the second patterned layer is comprised in a second substrate.
13 . The semiconductor package of claim 12 , wherein the first substrate is larger than the second substrate.
14 . The semiconductor package of claim 8 , wherein the one or more flexible electrical supports comprise a shape comprising one of a square, a rectangle, a closed hexagonal, an open rhomboid, a closed rhomboid, a circle, an oval, an ellipse, or any combination thereof.
15 . A semiconductor package comprising:
a first patterned layer;
a second patterned layer;
a first power die directly coupled to the first patterned layer and coupled between the first patterned layer and the second patterned layer;
a second power die directly coupled to the second patterned layer and coupled between the first patterned layer and the second patterned layer;
an electrical spacer coupled directly to the second patterned layer and coupled between the first power die and the second patterned layer; and
one or more flexible electrical supports directly coupled to the first patterned layer and the second patterned layer;
wherein the one or more flexible electrical supports are configured to bias the first patterned layer and the second patterned layer in a direction perpendicular to a surface of the first patterned layer directly coupled to the one or more flexible electrical supports when the one or more flexible electrical supports are compressed in a direction perpendicular to the surface of the first patterned layer directly coupled to the one or more flexible electrical supports.
16 . The semiconductor package of claim 15 , wherein each of the one or more flexible electrical supports are directly coupled to the first patterned layer and to the second patterned layer.
17 . The semiconductor package of claim 15 , wherein electrical spacer is directly coupled to the first power die.
18 . The semiconductor package of claim 15 , further comprising a second spacer coupled between the first patterned layer and the second patterned layer.
19 . The semiconductor package of claim 15 , the semiconductor package is a power module.
20 . The semiconductor package of claim 15 , wherein the first patterned layer is comprised in a first substrate having a perimeter larger than a perimeter of a second substrate comprising the second patterned layer.