IP Library Patent Application 19051470
Patent Application
App. No. 19/051,470

3D Co-Packaged Optics Stack

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Quick Facts
Patent No.
US None
App. No.
19/051,470
Abstract

A 3D co-packaged optics (CPO) stack device may include a thermal management and control layer, a printed circuit board (PCB) layer, a processing layer, a transimpedance amplifier and driver (TIA/Driver) electrical integrated circuit (EIC) layer, and a photonic integrated circuit (PIC) layer. The thermal management and control layer is positioned on a first surface of the PCB layer, a first surface of the processing layer is positioned on a second surface of the PCB layer, a first surface of the TIA/Driver EIC layer is positioned on a second surface of the processing layer, and a first surface of the PIC layer is positioned on a second surface of the TIA/Driver EIC layer.

Claims (69)

1 . A 3D co-packaged optics (CPO) stack device, comprising:

a thermal management and control layer;

a printed circuit board (PCB) layer;

a processing layer;

a transimpedance amplifier and driver (TIA/Driver) electrical integrated circuit (EIC) layer; and

a photonic integrated circuit (PIC) layer;

wherein the thermal management and control layer is positioned on a first surface of the PCB layer;

wherein a first surface of the processing layer is positioned on a second surface of the PCB layer, and wherein the second surface of the PCB layer is opposite the first surface of the PCB layer;

wherein a first surface of the TIA/Driver EIC layer is positioned on a second surface of the processing layer, and wherein the second surface of the processing layer is opposite the first surface of the processing layer; and

wherein a first surface of the PIC layer is positioned on a second surface of the TIA/Driver EIC layer, and wherein the second surface of the TIA/Driver EIC layer is opposite the first surface of the TIA/Driver EIC layer.

2 . The 3D CPO stack device of claim 1 , wherein the PIC layer comprises at least one of the following:

a plurality of laser devices;

a plurality of photodetectors (PDs);

a plurality of modulator devices; or

any combination thereof.

3 . The 3D CPO stack device of claim 1 , further comprising:

an optical interposer layer, wherein a first surface of the optical interposer layer is positioned on a second surface of the PIC layer, and wherein the second surface of the PIC layer is opposite the first surface of the PIC layer.

4 . The 3D CPO stack device of claim 3 , further comprising:

an optical fiber array coupled to the optical interposer layer.

5 . The 3D CPO stack device of claim 4 , wherein the optical fiber array is coupled to a second surface of the optical interposer layer, and wherein the second surface of the optical interposer layer is opposite the first surface of the optical interposer layer.

6 . The 3D CPO stack device of claim 4 , wherein a first end of the optical fiber array is coupled to the second surface of the optical interposer layer, the 3D CPO stack device further comprising:

at least one fiber connector coupled to a second end of the optical fiber array, wherein the at least one fiber connector provides a redirected path for light from an original path provided by the optical fiber array.

7 . The 3D CPO stack device of claim 3 , wherein the optical interposer layer comprises a plurality of layers of waveguides and a plurality of coupling elements, and wherein the plurality of coupling elements is configured to couple light between adjacent layers of waveguides of the plurality of layers of waveguides.

8 . The 3D CPO stack device of claim 1 , wherein the PIC layer is formed on the TIA/Driver EIC layer based on a flip-chip bonding procedure.

9 . The 3D CPO stack device of claim 1 , wherein the PIC layer is constructed based on at least one of the following:

a procedure involving silicon photonics (SiPho);

a procedure involving indium phosphide (InP);

a procedure involving Gallium Arsenide (GaAs); or

any combination thereof.

10 . The 3D CPO stack device of claim 1 , wherein the processing layer comprises an application specific integrated circuit (ASIC).

11 . The 3D CPO stack device of claim 10 , wherein the processing layer is constructed based on a procedure involving complementary metal-oxide-semiconductor (CMOS) ultra-large-scale Integration (ULSI).

12 . A 3D co-packaged optics (CPO) stack device, comprising:

a thermal management and control layer;

a printed circuit board (PCB) layer;

a processing layer;

a transimpedance amplifier and driver (TIA/Driver) electrical integrated circuit (EIC) layer; and

a laser and photodetector layer;

wherein the thermal management and control layer is positioned on a first surface of the PCB layer;

wherein a first surface of the processing layer is positioned on a second surface of the PCB layer, and wherein the second surface of the PCB layer is opposite the first surface of the PCB layer;

wherein a first surface of the TIA/Driver EIC layer is positioned on a second surface of the processing layer, and wherein the second surface of the processing layer is opposite the first surface of the processing layer; and

wherein a first surface of the laser and photodetector layer is positioned on a second surface of the TIA/Driver EIC layer, and wherein the second surface of the TIA/Driver EIC layer is opposite the first surface of the TIA/Driver EIC layer.

13 . The 3D CPO stack device of claim 12 , further comprising:

an optical interposer layer, wherein a first surface of the optical interposer layer is positioned on a second surface of the laser and photodetector layer, and wherein the second surface of the PIC layer is opposite the first surface of the laser and photodetector layer.

14 . The 3D CPO stack device of claim 12 , wherein the laser and photodetector layer comprises a plurality of laser devices, and wherein the plurality of laser devices comprises at least one of the following:

a vertical-cavity surface-emitting laser (VCSEL);

a quantum dot (QD) laser;

a light emitting diode laser;

a distributed feedback laser; or

any combination thereof.

15 . The 3D CPO stack device of claim 14 , wherein the laser and photodetector layer comprises a plurality of photodetectors (PDs), and wherein each laser device of the plurality of laser devices is driven by a separate driver transmission channel and each PD of the plurality of PDs is coupled to a separate transimpedance amplifier (TIA) and receiving channel.

16 . The 3D CPO stack device of claim 14 , wherein the laser and photodetector layer comprises a lens corresponding to each laser device of the plurality of laser devices to provide for collimation of light beams provided by the plurality of laser devices.

17 . The 3D CPO stack device of claim 14 , wherein the laser and photodetector layer is formed with the TIA/Driver EIC layer on the processing layer based on a flip-chip bonding procedure.

18 . A 3D co-packaged optics (CPO) stack device, comprising:

a thermal management and control layer;

a printed circuit board (PCB) layer;

a processing layer, wherein the processing layer receives control signals from the thermal management and control layer;

a transimpedance amplifier and driver (TIA/Driver) electrical integrated circuit (EIC) layer;

a photonic integrated circuit (PIC) layer;

an optical interposer layer, wherein the optical interposer layer comprises a plurality of vias that are configured to guide light through the optical interposer layer; and

an optical fiber array coupled to the optical interposer layer;

wherein the thermal management and control layer is positioned on a first surface of the PCB layer;

wherein a first surface of the processing layer is positioned on a second surface of the PCB layer, and wherein the second surface of the PCB layer is opposite the first surface of the PCB layer;

wherein a first surface of the TIA/Driver EIC layer is positioned on a second surface of the processing layer, and wherein the second surface of the processing layer is opposite the first surface of the processing layer;

wherein a first surface of the PIC layer is positioned on a second surface of the TIA/Driver EIC layer, and wherein the second surface of the TIA/Driver EIC layer is opposite the first surface of the TIA/Driver EIC layer; and

wherein a first surface of the optical interposer layer is positioned on a second surface of the PIC layer, and wherein the second surface of the PIC layer is opposite the first surface of the PIC layer.

19 . The 3D CPO stack device of claim 18 , wherein the optical fiber array is coupled to a second surface of the optical interposer layer, and wherein the second surface of the optical interposer layer is opposite the first surface of the optical interposer layer.

20 . The 3D CPO stack device of claim 19 , wherein a first end of the optical fiber array is coupled to the second surface of the optical interposer layer, the 3D CPO stack device further comprising:

a first fiber connector coupled to a first portion of the optical fiber array at a second end of the optical fiber array, wherein the first fiber connector provides a first redirected path for light from an original path provided by the optical fiber array; and

a second fiber connector coupled to a second portion of the optical fiber array at the second end of the optical fiber array, wherein the second fiber connector provides a second redirected path for light from an original path provided by the optical fiber array.

Assignments (2)
SECURITY INTEREST Recorded Oct 6, 2025
From: II-VI DELAWARE, INC.; COHERENT, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 072853/0806 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 13, 2025
From: CHEN, YOUNG-KAI; TATARCZAK, ANNA; KOCOT, CHRIS; BHATT, VIPUL; ENG, JULIE
To: II-VI DELAWARE, INC.
Reel/Frame 072007/0105 →