METHOD FOR SYNCHRONIZED SOFTWARE-IN-THE-LOOP (SIL) SIMULATION OF MULTI-COMPONENT SIMULATION MODELS

1 . A method for synchronized software-in-the-loop (SIL) simulation, comprising:

loading a first simulation component onto a computing farm with at least one computing module and a second simulation component onto an accelerator farm with at least one accelerator module, wherein the first simulation component is provided for a computer module, wherein the second simulation component is provided for an accelerator module, wherein the first simulation component is assigned a first simulation step size, wherein the second simulation component is assigned a second simulation step size shorter than the first simulation step size;

specifying a time master that triggers an execution of the first simulation component and the second simulation component, wherein a respective trigger initiates the execution of a respective simulation step comprising a time step of the first simulation component and a plurality of time steps of the second simulation component; and

performing the synchronized SIL simulation by repeatedly triggering simulation steps, wherein a respective new simulation step is triggered upon the first and second simulation components having finished calculations of a respective current simulation step.

2 . The method according to claim 1 , wherein the computer module is a processor, wherein the accelerator module is a programmable logic module, and wherein the second simulation component is implemented as a configuration bit stream.

3 . The method according to claim 2 , wherein the programmable logic module has a clock-enable input and at least a part of the programmable logic module implementing the second simulation component is stopped via the clock-enable input upon a desired number of clock cycles for the simulation step having been executed.

4 . The method according to claim 1 , wherein the computing module is a processor of a first instruction architecture; and

wherein the accelerator module comprises:

at least one computing core with parallel processing support;

at least one computing core for matrix calculations; and/or

a processor with a second instruction architecture which differs from the first instruction architecture.

5 . The method according to claim 1 , wherein the plurality of time steps of the second simulation component are determined from a ratio of a time step of the first simulation component to a time step of the second simulation component.

6 . The method according to claim 5 , wherein the time step of the first simulation component in a hardware-in-the-loop (HIL) system corresponds to a real time; and

wherein a discontinuous virtual time is used for an SIL simulation.

7 . The method according to claim 1 , wherein a majority of the plurality of time steps of the second simulation component are calculated synchronously to a fixed clock cycle of the accelerator module.

8 . The method according to claim 1 , wherein a separate process on a processor executing the first component is specified as the time master.

9 . A computer system, comprising:

a computing farm with at least one processor; and

an accelerator farm with at least one programmable logic module;

wherein the computing farm is configured to load a first simulation component;

wherein the accelerator farm is configured to load a second simulation component;

wherein the first simulation component is provided for a computer module, wherein the second simulation component is provided for an accelerator module, wherein the first simulation component is assigned a first simulation step size, wherein the second simulation component is assigned a second simulation step size shorter than the first simulation step size;

wherein the system further comprises a time master specified for the system, wherein the time master is configured to trigger an execution of the first simulation component and the second simulation component, wherein a respective trigger initiates the execution of a respective simulation step comprising a time step of the first simulation component and a plurality of time steps of the second simulation component; and

wherein the computing farm and the accelerator farm are configured to perform the synchronized SIL simulation based on repeated triggering of simulation steps, wherein a respective new simulation step is triggered upon the first and second simulation components having finished calculations of a respective current simulation step.

10 . A non-transitory computer-readable medium having processor-executable instructions for synchronized software-in-the-loop (SIL) simulation, wherein the processor-executable instructions, when executed, facilitate performance of the following:

loading a first simulation component onto a computing farm with at least one computing module and a second simulation component onto an accelerator farm with at least one accelerator module, wherein the first simulation component is provided for a computer module, wherein the second simulation component is provided for an accelerator module, wherein the first simulation component is assigned a first simulation step size, wherein the second simulation component is assigned a second simulation step size shorter than the first simulation step size;

specifying a time master that triggers an execution of the first simulation component and the second simulation component, wherein a respective trigger initiates the execution of a respective simulation step comprising a time step of the first simulation component and a plurality of time steps of the second simulation component; and

performing the synchronized SIL simulation by repeatedly triggering simulation steps, wherein a respective new simulation step is triggered upon the first and second simulation components having finished calculations of a respective current simulation step.