FABRICATION METHOD FOR JFET WITH IMPLANT ISOLATION
Methods and semiconductor devices are provided. A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region.
1 . A semiconductor device, comprising:
a semiconductor substrate of a first conductivity type and comprising a first surface and a second surface opposite to the first surface;
an active region comprising semiconductor fins of the first conductivity type;
a gate region of a second conductivity type opposite to the first conductivity type adjacent to side surfaces of the semiconductor fins;
an isolation region surrounding the active region;
an edge termination region surrounding the isolation region;
a body diode region interposed between the isolation region and the edge termination region;
a first conductor electrically coupled to the body diode region and the semiconductor fins;
a second conductor electrically coupled to the gate region; and
a third conductor adjacent to the second surface of the semiconductor substrate and electrically coupled the semiconductor fins and the body diode region.
2 . The semiconductor device of claim 1 wherein:
the semiconductor fins comprise a first III-nitride semiconductor material;
the gate region comprises a second III-nitride semiconductor material;
the gate region surrounds the semiconductor fins; and
the body diode region is within a portion of the gate region.
3 . The semiconductor device of claim 1 , wherein:
the isolation region comprises a first semiconductor fin; and
the first semiconductor fin is electrically decoupled from the first conductor.
4 . The semiconductor device of claim 1 , wherein:
the body diode region comprises a PN diode.
5 . The semiconductor device of claim 1 , wherein:
the body diode region comprises a Schottky diode.
6 . The semiconductor device of claim 1 , wherein:
the body diode region comprises a merged PIN Schottky diode.
7 . The semiconductor device of claim 1 , wherein:
the isolation region comprises a trench isolation.
8 . The semiconductor device of claim 1 , wherein:
the isolation region comprises an N-type doped region.
9 . A semiconductor device, comprising:
a substrate;
an active region comprising a plurality of semiconductor fins;
a source conductor electrically coupled to a surface of each of the plurality of semiconductor fins;
a gate region surrounding the semiconductor fins; and
a body diode surrounding the gate region,
wherein:
the plurality of semiconductor fins comprises a first III-nitride semiconductor material characterized by a first conductivity type; and
the gate region comprises a second III-nitride semiconductor material characterized by a second conductivity type opposite to the first conductivity type.
10 . The semiconductor device of claim 9 , further comprising:
an isolation region between the active region and the body diode; and
an edge termination region surrounding the body diode.
11 . The semiconductor device of claim 10 , wherein the isolation region comprises a trench.
12 . The semiconductor device of claim 10 , wherein the isolation region comprises a floating fin electrically decoupled from the source conductor.
13 . The semiconductor device of claim 10 , wherein the isolation region comprises an N-type doped region.
14 . The semiconductor device of claim 9 , wherein the body diode comprises:
a PN junction diode.
15 . The semiconductor device of claim 9 , wherein the body diode comprises:
a Schottky diode.
16 . The semiconductor device of claim 9 , wherein the body diode comprises:
a merged P-i-N Schottky (MPS) diode.
17 . A semiconductor device, comprising:
a substrate;
a III-nitride drift layer coupled to the substrate and characterized by a first conductivity type;
a plurality of III-nitride fins coupled to the III-nitride drift layer and characterized by the first conductivity type;
a III-nitride gate region surrounding the plurality of III-nitride fins and characterized by a second conductivity type opposite to the first conductivity type;
an integrated body diode surrounding the plurality of III-nitride fins; and
an isolation region between the plurality of III-nitride fins and the integrated body diode.
18 . The semiconductor device of claim 17 , wherein the integrated body diode is one of a PN diode, a Schottky diode, or a merged PIN Schottky diode.
19 . The semiconductor device of claim 17 , wherein the isolation region comprises one of a trench, a floating fin, or an n-type doped region.
20 . The semiconductor device of claim 17 , further comprising:
an edge termination region surrounding the integrated body diode;
wherein:
the substrate comprises a III-nitride semiconductor material.