LATERAL III-NITRIDE DEVICES INCLUDING A VERTICAL GATE MODULE
A lateral III-N device has a vertical gate module with III-N material orientated in an N-polar or a group-III polar orientation. A III-N material structure has a III-N buffer layer, a III-N barrier layer, and a III-N channel layer. A compositional difference between the III-N barrier layer and the III-N channel layer causes a 2DEG channel to be induced in the III-N channel layer. A p-type III-N body layer is disposed over the III-N channel layer in a source side access region but not over a drain side access region. A n-type III-N capping layer over the p-type III-N body layer. A source electrode that contacts the n-type III-N capping layer is electrically connected to the p-type III-N body layer and is electrically isolated from the 2DEG channel when the gate electrode is biased relative to the source electrode at a voltage that is below a threshold voltage.
1 . An electronic device, comprising:
an N-polar III-N material structure, wherein the III-N material structure comprises a III-N channel layer, a p-type GaN body layer, and an n-type GaN capping layer;
a gate contact between a source contact and a drain contact, wherein the p-type GaN body layer is between the source contact and the III-N channel layer and the drain contact is electrically connected to the III-N channel layer; and
a III-N layer structure between the gate contact and a sidewall of the p-type GaN body layer; wherein
the III-N layer structure contacts the n-type GaN capping layer in a first region between the source contact and the gate contact and contacts the III-N channel layer in a second region between the gate contact and the drain contact.
2 . The device of claim 1 , wherein the III-N layer structure is continuous between the source and drain contact.
3 . The device of claim 1 , wherein the III-N layer structure comprises a GaN layer.
4 . The device of claim 3 , wherein the III-N layer structure further comprises an Al y Ga 1-y N layer, wherein y is greater than 0.5.
5 . The device of claim 3 , wherein the thickness of the GaN layer is between 2 nm and 10 nm.
6 . The device of claim 1 , wherein the sheet-resistance of the n-type GaN capping layer is lower than the sheet-resistance of the III-N channel layer.
7 . The device of claim 1 , wherein the p-type GaN body layer has a thickness between 2 nm and 5 μm and a doping density less than 5×10 19 cm −3 .
8 . The device of claim 1 , wherein the thickness of the III-N channel layer in the second region is less than the thickness of the III-N channel layer in the first region.
9 . The device of claim 1 , wherein the composition of the III-N channel layer is graded such that the gradient of the polarization field is negative in the [0 0 0 −1] direction.
10 . The device of claim 1 , wherein the III-N material structure further comprises a III-N back-barrier layer where the III-N channel layer is between the p-type GaN body layer and the III-N back-barrier layer.
11 . The device of claim 10 , wherein the III-N back-barrier layer comprises a first portion, a second portion and a third portion; wherein
the first portion comprises n-type GaN, the second portion comprises AlGaN with a varying composition, and the third portion comprises AlGaN with a constant composition.
12 . The device of claim 11 , wherein the first potion of the III-N back-barrier layer is doped with silicon.
13 . An electronic device, comprising:
an N-polar III-N material structure comprising a first n-type GaN layer with a first doping density over a first p-type GaN layer with a second doping density; and
an electrode at least partially over the n-type GaN layer; wherein
the electrode is electrically connected to the p-type layer through a tunnel junction; and
the tunnel junction comprises an Al y Ga 1-y N layer with 0<y≤1 at an interface between the p-type GaN layer and the n-type GaN layer.
14 . The device of claim 13 , further comprising a recess in the n-type layer, wherein the electrode is at least partially in the recess.
15 . The device of claim 14 , wherein at least a portion of the recess extends to a top surface of the p-type GaN layer, and a portion of the electrode is directly contacting the p-type GaN layer, wherein the tunnel junction is formed between the electrode and the p-type GaN layer through a sidewall of the recess in the n-type layer.
16 . The device of claim 13 , wherein y is greater than 0.5, and the thickness of Al y Ga 1-y N layer is between 0.5 nm and 5 nm.
17 . The device of claim 16 , wherein the tunnel junction further comprises a second n-type GaN layer between the first n-type GaN layer and the Al y Ga 1-y N layer, and a second p-type GaN layer between the first p-type GaN layer and the Al y Ga 1-y N layer, wherein the second n-type GaN layer and the second p-type GaN layer have a doping density greater than the first and second doping densities.
18 . The device of claim 17 , wherein the second p-type GaN layer and the second n-type GaN layer each have a thickness between 2 nm and 50 nm and a doping density greater than 5×10 19 cm −3 .
19 . The device of claim 18 , wherein the first p-type GaN layer has a thickness between 2 nm and 5 μm and a doping density less than 5×10 19 cm −3 .
20 . A method of operating a III-N device, the method comprising:
biasing a gate contact relative to a source contact at a voltage greater than a threshold voltage, wherein an inversion channel forms at a slanted or vertical interface between a gate insulator layer and a p-type III-N layer, thereby electrically connecting the source contact to a lateral 2DEG channel; and
biasing a drain contact at a positive voltage relative to the source contact; wherein
electrons flow from the source contact through the inversion channel, and into the lateral 2DEG channel; and
a continuous device channel is formed between the source contact and the drain contact.
21 . The method of claim 20 , the method further comprising:
biasing the gate contact relative to the source contact at a voltage less than the threshold voltage; wherein the p-type III-N layer fully depletes any charge at the slanted or vertical interface between the p-type III-N layer and the gate insulator layer such that there is no inversion channel and the device channel is discontinuous between the source contact and the lateral 2DEG channel.
22 . The method of claim 21 , the method further comprising:
biasing the drain contact at a positive voltage greater than a minimum voltage; wherein the 2DEG channel is fully depleted of charge in a source side access region.
23 . The method of claim 22 , wherein the minimum voltage is less than 10V.