Method and apparatus for dma between accelerator cards, and accelerator card, acceleration platform and medium
A method and apparatus of direct memory access DMA between accelerator cards, an accelerator card, an accelerating platform and a non-volatile readable storage medium. The first accelerator card according to the present application can initiatively perform the initiation of the DMA, and, according to the idle-internal-memory datum of the second accelerator card as the data destination terminal recorded in the first accelerator card itself, write the datum directly into the internal memory of the second accelerator card in the mode of DMA, which does not require inquiring the idle-internal-memory address of the second accelerator card before the DMA, and does not require waiting for the second accelerator card to initiate the DMA. The solution realizes the direct DMA writing operation between different accelerator cards at the hardware level, and solves the problem in DMA operation between accelerator cards.
1 . A method of direct memory access DMA between accelerator cards, wherein the method is applied in a first accelerator card in a mainframe-free accelerating platform, and comprises:
in response to an acceleration task having been executed to obtain a to-be-transmitted datum, according to idle internal-memory capacities and accelerator-card functions, determining a second accelerator card in the accelerating platform configured for processing the to-be-transmitted datum, wherein each of accelerator cards in the accelerating platform is provided with a direct-memory-access controller, and the first accelerator card and the second accelerator card are connected by an expansion chip;
inquiring an idle-internal-memory datum of the second accelerator card in the first accelerator card itself, wherein the second accelerator card broadcasts the idle-internal-memory datum in the accelerating platform in response to the idle internal-memory capacity being greater than a preset threshold; and
initiatively initiating DMA, to, by using the direct-memory-access controller of the first accelerator card itself and the idle-internal-memory datum, write the to-be-transmitted datum into an internal memory of the second accelerator card in a mode of direct memory access.
2 . The method according to claim 1 , wherein the step of, according to the idle internal-memory capacities and the accelerator-card functions, determining the second accelerator card in the accelerating platform configured for processing the to-be-transmitted datum comprises:
preestimating a data-volume size of the to-be-transmitted datum; and
determining the second accelerator card that has a function of processing the to-be-transmitted datum and the idle internal-memory capacity of which is not less than the data-volume size.
3 . The method according to claim 2 , wherein the step of determining the second accelerator card that has the function of processing the to-be-transmitted datum and the idle internal-memory capacity of which is not less than the data-volume size comprises:
inquiring data processing functions of the other accelerator cards than the first accelerator card in the accelerating platform, and selecting a candidate accelerator card the data processing function of which is the same as a next-step processing function of the to-be-transmitted datum; and
determining at least one instance of the candidate accelerator card the idle internal-memory capacity of which is not less than the data-volume size to be the second accelerator card.
4 . The method according to claim 1 , wherein the method further comprises:
preestimating an internal-memory amount required by the execution of the acceleration task, and in response to a difference between a current idle internal-memory capacity of the first accelerator card itself and the internal-memory amount being greater than a preset threshold, broadcasting a storage-resource-usage datum of the first accelerator card itself to the other accelerator cards than the first accelerator card in the accelerating platform.
5 . The method according to claim 1 , wherein the method further comprises:
receiving storage-resource-usage data broadcasted by the other accelerator cards than the first accelerator card in the accelerating platform, wherein each of the other accelerator cards broadcasts the storage-resource-usage datum containing the idle-internal-memory datum in the accelerating platform in response to the idle internal-memory capacity being greater than the preset threshold; and
according to the storage-resource-usage data, updating the idle-internal-memory data of the other accelerator cards that the first accelerator card itself stores.
6 . The method according to claim 1 , wherein the step of, by using the direct-memory-access controller of the first accelerator card itself and the idle-internal-memory datum, writing the to-be-transmitted datum into the internal memory of the second accelerator card in the mode of direct memory access comprises:
by using the direct-memory-access controller of the first accelerator card itself, according to the idle-internal-memory datum and a memory address occupied by the to-be-transmitted datum in the first accelerator card itself, constructing descriptor information;
according to the descriptor information, constructing the to-be-transmitted datum into a first message; and
sending the first message to the second accelerator card, whereby the second accelerator card writes the to-be-transmitted datum in the first message into the internal memory of the second accelerator card itself.
7 . The method according to claim 6 , wherein the step of, by the second accelerator card, writing the to-be-transmitted datum in the first message into the internal memory of the second accelerator card itself comprises:
by the second accelerator card, in response to the second accelerator card having determined that a data-writing address of the first message falls within a memory-address range, writing the to-be-transmitted datum in the first message into the internal memory of the second accelerator card itself.
8 . The method according to claim 1 , wherein the method further comprises:
receiving a second message and converting the second message into a target format;
in response to it being determined that a data-writing address of the second message falls within a register-address range, writing a datum in the second message into a register of the first accelerator card itself; and
by using the datum in the register, configuring an entry of an address mapping table, and/or modifying a period of broadcasting of a storage-resource-usage datum.
9 . The method according to claim 8 , wherein the method further comprises:
in response to it being determined that the data-writing address of the second message falls within a memory-address range, writing the datum in the second message into an internal memory of the first accelerator card itself.
10 . The method according to claim 8 , wherein the method further comprises:
receiving a direct-memory-access request sent by an external mainframe;
inquiring, in the address mapping table, a memory address corresponding to a virtual address in the direct-memory-access request; and
according to the memory address, completing the direct-memory-access request.
11 . The method according to claim 1 , wherein a downstream interface of the first accelerator card is a root-device-mode interface or slave-device-mode interface that supports a serial computer expansion bus standard, and a bus-address range of the downstream interface is not less than a bus-address range of a downstream device connected thereto.
12 . The method according to claim 11 , wherein the downstream interface is configured by:
by using an upstream interface of the first accelerator card, receiving a configuring message of the downstream interface;
converting the configuring message into a second message that meets the serial computer expansion bus standard;
according to the second message, configuring the bus-address range of the downstream device, and configuring identifier information for the downstream device; and
according to the second message, performing bus-address configuring to a root-device core or slave-device core of the downstream interface, whereby the bus-address range of the downstream interface is not less than the bus-address range of the downstream device.
13 . The method according to claim 12 , wherein before the step of, according to the second message, performing bus-address configuring to the slave-device core of the downstream interface, the method further comprises converting the second message into a data format that matches with the slave-device mode.
14 . The method according to claim 11 , wherein the downstream interface is a plurality of downstream interfaces; and
the method further comprises:
receiving a data message sent by a downstream device connected to any instance of the downstream interfaces;
in response to a destination address of the data message being not within a network route window, determining whether the destination address of the data message is within a forwarding route window of the other downstream interfaces; and
in response to the destination address of the data message being within a forwarding route window of a destination interface, via the destination interface, forwarding the data message to a downstream device connected to the destination interface, wherein the destination interface refers to at least one of the other downstream interfaces.
15 . An accelerating platform, wherein the accelerating platform comprises a plurality of accelerator cards, and the different instances of the accelerator cards are connected by expansion chips;
each of the accelerator cards is provided with a direct-memory-access controller, a storage-resource register, a selecting module and an internal memory;
the selecting module, according to idle internal-memory capacities and accelerator-card functions, determines another accelerator card configured for processing a to-be-transmitted datum obtained by execution of an acceleration task, and inquires an idle-internal-memory datum of the another accelerator card;
the another accelerator card broadcasts the idle-internal-memory datum in the accelerating platform in response to the idle internal-memory capacity being greater than a preset threshold;
the storage-resource register stores the idle-internal-memory datum of the another accelerator card; and
the direct-memory-access controller initiatively initiates DMA, to, according to the idle-internal-memory datum, write the to-be-transmitted datum into the internal memory of the another accelerator card in a mode of direct memory access.
16 . The accelerating platform according to claim 15 , wherein the selecting module further comprises a preestimating unit and a selecting unit;
the preestimating unit preestimates a data-volume size of the to-be-transmitted datum; and
the selecting unit inquires data processing functions of other accelerator cards, and selects an accelerator card the data processing function of which is the same as a next-step processing function of the to-be-transmitted datum and the idle internal-memory capacity of which is not less than the data-volume size.
17 . The accelerating platform according to claim 15 , wherein each of the accelerator cards is further provided with a resource-sharing module, the resource-sharing module preestimates an internal-memory amount required by the execution of the acceleration task, and in response to a difference between the idle internal-memory capacity of the internal memory and the internal-memory amount being greater than a preset threshold, broadcasts a storage-resource-usage datum of the internal memory to the other accelerator cards;
in response to the accelerator card being in an idle state, in response to the idle internal-memory capacity of the internal memory being greater than a preset threshold, the resource-sharing module broadcasts the storage-resource-usage datum of the internal memory to the other accelerator cards; and
the resource-sharing module receives the storage-resource-usage data containing the idle-internal-memory data that are broadcasted by the other accelerator cards in the accelerating platform in response to the idle internal-memory capacity being greater than the preset threshold, and, according to the storage-resource-usage data, updates the idle-internal-memory data of the other accelerator cards that the storage-resource register stores.
18 . An accelerator card, wherein the accelerator card is provided with a direct-memory-access controller, a storage-resource register, a selecting module and an internal memory;
the selecting module, according to idle internal-memory capacities and accelerator-card functions, determines another accelerator card configured for processing a to-be-transmitted datum obtained by execution of an acceleration task, and inquires an idle-internal-memory datum of the another accelerator card;
the another accelerator card broadcasts the idle-internal-memory datum in the accelerating platform in response to the idle internal-memory capacity being greater than a preset threshold;
the different accelerator cards are connected by an expansion chip;
the storage-resource register stores the idle-internal-memory datum of the another accelerator card; and
the direct-memory-access controller initiatively initiates DMA, to, according to the idle-internal-memory datum, write the to-be-transmitted datum into the internal memory of the another accelerator card in a mode of direct memory access.
19 . The accelerator card according to claim 18 , wherein the accelerator card is an FPGA (Field Programmable Gate Array) accelerator card, an ASIC (Application Specific Integrated Circuit) accelerator card or a multi-core processor.
20 . A non-transitory readable storage medium, wherein the non-transitory readable storage medium is configured for storing a computer program, and the computer program, when executed by a processor, implements the method according to claim 1 .