DECISION FEEDBACK EQUALIZATION TAPS AND RELATED APPARATUSES AND METHODS
Decision feedback equalization (DFE) taps and related apparatuses and methods are disclosed. An apparatus includes a first electrically controllable switch, a second electrically controllable switch, and one or more delay elements. The first electrically controllable switch receives a history bit and selectively provides the history bit to gate terminals of first transistors of a DFE tap circuitry. The second electrically controllable switch receives a complementary history bit and selectively provides the complementary history bit to second gate terminals of second transistors of the DFE tap circuitry. The one or more delay elements provide one or more delayed data integration clock signals responsive to one or more data integration clock signals. A complementary delayed data integration clock signal controls switching of the first electrically controllable switch and the second electrically controllable switch.
1 - 15 . (canceled)
16 . A method of controlling a decision feedback equalization (DFE) tap circuitry, the method comprising:
delaying, with a gating circuitry, data integration clock signals to provide delayed data integration clock signals;
providing, with the gating circuitry, a previous history bit and a previous complementary history bit at first logic levels to gate terminals of transistors of the DFE tap circuitry responsive to the delayed data integration clock signals;
electrically isolating, with the gating circuitry, the gate terminals from the previous history bit and the previous complementary history bit responsive to the delayed data integration clock signals;
providing, with the gating circuitry, a common mode voltage potential to the gate terminals prior to a transition from the previous history bit and the previous complementary history bit at the first logic levels to a history bit and a complementary history bit at second logic levels;
triggering a start of a reset state responsive to the data integration clock signals; and
triggering a start of a tap integration state and delivering the history bit and the complementary history bit at the second logic levels to the gate terminals responsive to the delayed data integration clock signals.
17 . The method of claim 16 , comprising sampling a data signal responsive to a data sampling clock signal.
18 . The method of claim 17 , comprising ending the tap integration state and the data integration clock signals responsive to the data sampling clock signal.
19 . The method of claim 17 , wherein one of the data integration clock signals is substantially ninety degrees out of phase with the data sampling clock signal.
20 . The method of claim 16 , wherein delaying the data integration clock signals comprises delaying the data integration clocks signals with delay elements of the gating circuitry, the delay elements including strings of logic gates.
21 . The method of claim 16 , wherein providing the common mode voltage potential to the gate terminals comprises electrically connecting the gate terminals to a common mode voltage potential node responsive to one of the delayed data integration clock signals.
22 . An apparatus comprising:
a gating circuitry to control a decision feedback equalization (DFE) tap circuitry, the gating circuitry to:
delay data integration clock signals to provide delayed data integration clock signals;
provide a previous history bit and a previous complementary history bit at first logic levels to gate terminals of transistors of the DFE tap circuitry responsive to the delayed data integration clock signals;
electrically isolate the gate terminals from the previous history bit and the previous complementary history bit responsive to the delayed data integration clock signals; and
provide a common mode voltage potential to the gate terminals prior to a transition from the previous history bit and the previous complementary history bit at the first logic levels to a history bit and a complementary history bit at second logic levels,
wherein a start of a reset state of the DFE tap circuitry is triggered responsive to the data integration clock signals, and
wherein a start of a tap integration state of the DFE tap circuitry is triggered and the history bit and the complementary history bit are delivered at the second logic levels to the gate terminals responsive to the delayed data integration clock signals.
23 . The apparatus of claim 22 , wherein:
the gating circuitry is to end the tap integration state and the data integration clock signals responsive to a data sampling clock signal used to sample a data signal.
24 . The apparatus of claim 23 , wherein one of the data integration clock signals is substantially ninety degrees out of phase with the data sampling clock signal.
25 . The apparatus of claim 22 , wherein:
the gating circuitry includes delay elements to delay the data integration clock signals, the delay elements including strings of logic gates.
26 . The apparatus of claim 22 , wherein:
the gating circuitry is to provide the common mode voltage potential to the gate terminals by electrically connecting the gate terminals to a common mode voltage potential node responsive to one of the delayed data integration clock signals.
27 . The apparatus of claim 22 , wherein:
the gating circuitry is to hold the DFE tap circuitry in the reset state until after arrival of the history bit to avoid integrating the previous history bit.
28 . The apparatus of claim 22 , wherein:
the gating circuitry is to delay the data integration clock signals to align with arrival of the history bit.
29 . An apparatus comprising:
a decision feedback equalization (DFE) tap circuitry, the DFE tap circuitry including at least a pair of transistors, the pair of transistors including gate terminals, the pair of transistors including drain terminals electrically connected to output nodes of the DFE tap circuitry; and
a gating circuitry to control the DFE tap circuitry, the gating circuitry to:
delay data integration clock signals to provide delayed data integration clock signals;
provide a previous history bit and a previous complementary history bit at first logic levels to the gate terminals of the pair of transistors responsive to the delayed data integration clock signals;
electrically isolate the gate terminals of the pair of transistors from the previous history bit and the previous complementary history bit responsive to the delayed data integration clock signals; and
provide a common mode voltage potential to the gate terminals of the pair of transistors prior to a transition from the previous history bit and the previous complementary history bit at the first logic levels to a history bit and a complementary history bit at second logic levels,
wherein the DFE tap circuitry is placed in a reset state responsive to the data integration clock signals, and
wherein the DFE tap circuitry is placed in a tap integration state, and the history bit and the complementary history bit are delivered at the second logic levels to the gate terminals of the pair of transistors, responsive to the delayed data integration clock signals.
30 . The apparatus of claim 29 , wherein:
the gating circuitry is to end the tap integration state and the data integration clock signals responsive to a data sampling clock signal used to sample a data signal.
31 . The apparatus of claim 30 , wherein one of the data integration clock signals is substantially ninety degrees out of phase with the data sampling clock signal.
32 . The apparatus of claim 29 , wherein:
the gating circuitry includes delay elements to delay the data integration clock signals, the delay elements including strings of logic gates.
33 . The apparatus of claim 29 , wherein:
the gating circuitry is to provide the common mode voltage potential to the gate terminals by electrically connecting the gate terminals to a common mode voltage potential node responsive to one of the delayed data integration clock signals.
34 . The apparatus of claim 29 , wherein:
the gating circuitry is to hold the DFE tap circuitry in the reset state until after arrival of the history bit to avoid integrating the previous history bit.
35 . The apparatus of claim 29 , wherein:
the gating circuitry is to delay the data integration clock signals to align with arrival of the history bit.