DEEP VISION PROCESSOR
Disclosed herein is a processor for deep learning. In one embodiment, the processor comprises: a load and store unit configured to load and store image pixel data and stencil data; a register unit, implementing a banked register file, configured to: load and store a subset of the image pixel data from the load and store unit, and concurrently provide access to image pixel values stored in a register file entry of the banked register file, wherein the subset of the image pixel data comprises the image pixel values stored in the register file entry; and a plurality of arithmetic logic units configured to concurrently perform one or more operations on the image pixel values stored in the register file entry and corresponding stencil data of the stencil data.
1 . A processor comprising:
a register file:
comprising a set of banks; and
configured to store image data;
an interconnect unit configured to:
access a set of image data stored in the register file; and
access a set of stencil data for the set of image data; and
a set of logic units:
in communication with the interconnect unit;
configured to execute a set of stencil operations on the set of image data and the set of stencil data, the set of stencil spanning a first size range and characterized by at least two-dimensions; and
configured to execute a set of convolution operations on the set of the image data and the stencil data, the set of convolution operations spanning a second size range different from than the first size range.
2 . The processor of claim 1 , wherein the register file represents a two-dimensional register abstraction.