CIRCUIT DESIGN USING A BOOLEAN SATISFIABILITY SOLVER

1 . A method of electronic design automation performed by one or more computers, the method comprising:

accessing, by the one or more computers, circuit data describing circuit behavior or logic for a circuit to be designed;

generating, by the one or more computers, one or more Boolean expressions with variables that each represent a different design characteristic for the circuit, wherein, for each of at least some of the variables, the variable represents a decision whether a connection is made between a corresponding pair of nodes in the circuit;

defining, by the one or more computers, a Boolean satisfiability problem for the class of circuits having a predetermined circuit size, wherein the Boolean satisfiability problem has criteria that include (i) the generated one or more Boolean expressions and (ii) an assertion that the circuit is faulted;

using, by the one or more computers, a Boolean satisfiability solver to process the Boolean satisfiability problem;

after the Boolean satisfiability solver indicates that the Boolean satisfiability problem is unsatisfiable, using, by the one or more computers, the Boolean satisfiability solver to solve a series of updated versions of the Boolean satisfiability problem,

wherein the updated versions of the Boolean satisfiability problem progressively reduce the circuit size compared to the previous version of the Boolean satisfiability problem while maintaining a search space of the Boolean satisfiability problem, and

wherein the Boolean satisfiability solver is configured to store analysis results for the search space and to use the stored analysis results to perform the updated versions of the Boolean satisfiability problem; and

generating, by the one or more computers, circuit design parameters for the circuit based on results of a processing iteration for which the corresponding version of the Boolean satisfiability problem is determined to be unsatisfiable based on the processing of the Boolean satisfiability solver.

2 . The method of claim 1 , wherein using the Boolean satisfiability solver to solve the series of updated versions of the Boolean satisfiability problem comprises:

processing updated versions of the Boolean satisfiability problem for progressively smaller circuit sizes until obtaining a result for an updated version of the Boolean satisfiability problem that is indicated to be satisfiable based on the processing of the Boolean satisfiability solver;

wherein the generated circuit design parameters comprise a circuit design determined for the smallest circuit size for which the corresponding updated version of the Boolean satisfiability problem is determined to be unsatisfiable.

3 . The method of claim 1 , wherein the updated versions of the Boolean satisfiability problem each add an assertion that an additional element of the circuit is disconnected or unused.

4 . The method of claim 1 , wherein the predetermined circuit size is a predetermined number of transistors or logic gates; and

wherein the series of updated versions of the Boolean satisfiability problem is a series of series of updated versions of the Boolean satisfiability problem that respectively include assertions that progressively greater numbers of transistors or logic gates, of the predetermined number of transistors or logic gates, be disconnected or unused.

5 . The method of claim 1 , wherein generating the circuit design parameters comprises selecting a circuit size corresponding to the processing iteration for the smallest circuit size for which the corresponding updated version of the Boolean satisfiability problem is determined to be unsatisfiable.

6 . The method of claim 1 , wherein generating the circuit design parameters comprises:

identifying, for the processing iteration for the smallest circuit size for which the corresponding updated version of the Boolean satisfiability problem is determined to be unsatisfiable, a combination of values for the variables of the Boolean expressions for the corresponding Boolean satisfiability problem that does not satisfy the assertion that the circuit is faulted; and

generating data indicating a set of connections among nodes in the circuit based on the identified combination of values.

7 . The method of claim 1 , wherein the circuit data comprises combinatorial logic for the circuit or a truth table for the circuit.

8 . The method of claim 1 , wherein the assertion that the circuit is faulted is a requirement that the Boolean satisfiability problem is satisfiable only if there is no combination of values for the variables for which all combinations of the inputs would produce the circuit behavior or logic indicated by the circuit data.

9 . The method of claim 1 , wherein using the Boolean satisfiability solver to process the Boolean satisfiability problem comprises:

evaluating different combinations of values for the variables representing different design characteristics, including, for each combination of values of the different combinations of values:

evaluating multiple combinations of circuit input values to determine whether, for a circuit having the set of design characteristics indicated by the combination values, each of the multiple combinations of circuit input values would result in circuit output that is specified for the circuit by the circuit data.

10 . The method of claim 1 , comprising:

accessing a set of design rules for the circuit; and

using the design rules to (i) generate one or more of the Boolean expressions in the sets of Boolean expressions or (ii) limit a set of combinations of values for the variables of the Boolean expressions.

11 . A system comprising:

one or more computers; and

one or more computer-readable media storing instructions that are operable, when executed by the one or more computers, to cause the system to perform operations comprising:

accessing, by the one or more computers, circuit data describing circuit behavior or logic for a circuit to be designed;

generating, by the one or more computers, one or more Boolean expressions with variables that each represent a different design characteristic for the circuit, wherein, for each of at least some of the variables, the variable represents a decision whether a connection is made between a corresponding pair of nodes in the circuit;

defining, by the one or more computers, a Boolean satisfiability problem for the class of circuits having a predetermined circuit size, wherein the Boolean satisfiability problem has criteria that include (i) the generated one or more Boolean expressions and (ii) an assertion that the circuit is faulted;

using, by the one or more computers, a Boolean satisfiability solver to process the Boolean satisfiability problem;

after the Boolean satisfiability solver indicates that the Boolean satisfiability problem is unsatisfiable, using, by the one or more computers, the Boolean satisfiability solver to solve a series of updated versions of the Boolean satisfiability problem,

wherein the updated versions of the Boolean satisfiability problem progressively reduce the circuit size compared to the previous version of the Boolean satisfiability problem while maintaining a search space of the Boolean satisfiability problem, and

wherein the Boolean satisfiability solver is configured to store analysis results for the search space and to use the stored analysis results to perform the updated versions of the Boolean satisfiability problem; and

generating, by the one or more computers, circuit design parameters for the circuit based on results of a processing iteration for which the corresponding version of the Boolean satisfiability problem is determined to be unsatisfiable based on the processing of the Boolean satisfiability solver.

12 . The system of claim 11 , wherein using the Boolean satisfiability solver to solve the series of updated versions of the Boolean satisfiability problem comprises:

processing updated versions of the Boolean satisfiability problem for progressively smaller circuit sizes until obtaining a result for an updated version of the Boolean satisfiability problem that is indicated to be satisfiable based on the processing of the Boolean satisfiability solver;

wherein the generated circuit design parameters comprise a circuit design determined for the smallest circuit size for which the corresponding updated version of the Boolean satisfiability problem is determined to be unsatisfiable.

13 . The system of claim 11 , wherein the updated versions of the Boolean satisfiability problem each add an assertion that an additional element of the circuit is disconnected or unused.

14 . The system of claim 11 , wherein the predetermined circuit size is a predetermined number of transistors or logic gates; and

wherein the series of updated versions of the Boolean satisfiability problem is a series of series of updated versions of the Boolean satisfiability problem that respectively include assertions that progressively greater numbers of transistors or logic gates, of the predetermined number of transistors or logic gates, be disconnected or unused.

15 . The system of claim 11 , wherein generating the circuit design parameters comprises selecting a circuit size corresponding to the processing iteration for the smallest circuit size for which the corresponding updated version of the Boolean satisfiability problem is determined to be unsatisfiable.

16 . The system of claim 11 , wherein generating the circuit design parameters comprises:

identifying, for the processing iteration for the smallest circuit size for which the corresponding updated version of the Boolean satisfiability problem is determined to be unsatisfiable, a combination of values for the variables of the Boolean expressions for the corresponding Boolean satisfiability problem that does not satisfy the assertion that the circuit is faulted; and

generating data indicating a set of connections among nodes in the circuit based on the identified combination of values.

17 . The system of claim 11 , wherein the circuit data comprises combinatorial logic for the circuit or a truth table for the circuit.

18 . The system of claim 11 , wherein the assertion that the circuit is faulted is a requirement that the Boolean satisfiability problem is satisfiable only if there is no combination of values for the variables for which all combinations of the inputs would produce the circuit behavior or logic indicated by the circuit data.

19 . The system of claim 11 , wherein using the Boolean satisfiability solver to process the Boolean satisfiability problem comprises:

evaluating different combinations of values for the variables representing different design characteristics, including, for each combination of values of the different combinations of values:

evaluating multiple combinations of circuit input values to determine whether, for a circuit having the set of design characteristics indicated by the combination values, each of the multiple combinations of circuit input values would result in circuit output that is specified for the circuit by the circuit data.

20 . One or more non-transitory computer-readable media storing instructions that are operable, when executed by one or more computers, to cause the one or more computers to perform operations comprising:

accessing, by the one or more computers, circuit data describing circuit behavior or logic for a circuit to be designed;

generating, by the one or more computers, one or more Boolean expressions with variables that each represent a different design characteristic for the circuit, wherein, for each of at least some of the variables, the variable represents a decision whether a connection is made between a corresponding pair of nodes in the circuit;

defining, by the one or more computers, a Boolean satisfiability problem for the class of circuits having a predetermined circuit size, wherein the Boolean satisfiability problem has criteria that include (i) the generated one or more Boolean expressions and (ii) an assertion that the circuit is faulted;

using, by the one or more computers, a Boolean satisfiability solver to process the Boolean satisfiability problem;

after the Boolean satisfiability solver indicates that the Boolean satisfiability problem is unsatisfiable, using, by the one or more computers, the Boolean satisfiability solver to solve a series of updated versions of the Boolean satisfiability problem,

wherein the updated versions of the Boolean satisfiability problem progressively reduce the circuit size compared to the previous version of the Boolean satisfiability problem while maintaining a search space of the Boolean satisfiability problem, and

wherein the Boolean satisfiability solver is configured to store analysis results for the search space and to use the stored analysis results to perform the updated versions of the Boolean satisfiability problem; and

generating, by the one or more computers, circuit design parameters for the circuit based on results of a processing iteration for which the corresponding version of the Boolean satisfiability problem is determined to be unsatisfiable based on the processing of the Boolean satisfiability solver.