SIGNAL DEVELOPMENT CACHING IN A MEMORY DEVICE
Methods, systems, and devices for signal development caching in a memory device are described. In one example, a memory device in accordance with the described techniques may include a memory array, a sense amplifier array, and a signal development cache configured to store signals (e.g., cache signals, signal states) associated with logic states (e.g., memory states) that may be stored at the memory array (e.g., according to various read or write operations). In various examples, accessing the memory device may include accessing information from the signal development cache, or the memory array, or both, based on various mappings or operations of the memory device.
1 . (canceled)
2 . A method, comprising:
determining to store a respective cache signal, for each of a plurality of logic states for writing to a plurality of memory cells of a memory array, at a respective storage element of a plurality of storage elements of a signal development cache;
coupling, based at least in part on the determining, a plurality of sense amplifiers of a sense amplifier array to the plurality of storage elements of the signal development cache to store the respective cache signal for each of the plurality of logic states to the respective storage element;
coupling, after storing the respective cache signal for each of the plurality of logic states to the respective storage element, the plurality of storage elements with the plurality of memory cells; and
writing the plurality of logic states to the plurality of memory cells of the memory array based at least in part on coupling the plurality of storage elements with the plurality of memory cells.
3 . The method of claim 2 , wherein storing the respective cache signal for each of the plurality of logic states at the respective storage element of the signal development cache comprises:
coupling, during a first time interval, a first sense amplifier of the sense amplifier array with a first storage element of the plurality of storage elements; and
coupling, during second time interval that follows the first time interval, the first sense amplifier of the sense amplifier array with a second storage element of the plurality of storage elements.
4 . The method of claim 3 , wherein coupling the plurality of storage elements with the plurality of memory cells comprises:
coupling, during a third time interval, the first storage element of the plurality of storage elements with a first memory cell of the plurality of memory cells; and
coupling, during a fourth time interval that overlaps the third time interval, the second storage element of the plurality of storage elements with a second memory cell of the plurality of memory cells.
5 . The method of claim 2 , wherein the memory array comprises a plurality of domains each associated with a respective subset of a plurality of word lines, the method further comprising:
activating a word line of a first domain of the plurality of domains to couple a first subset of the plurality of memory cells with a first subset of the plurality of storage elements; and
activating a word line of a second domain of the plurality of domains to couple a second subset of the plurality of memory cells with a second subset of the plurality of storage elements.
6 . The method of claim 5 , wherein each of the plurality of domains is associated with one or more of a plurality of plate nodes that are each operable to be biased independent of other plate nodes of the plurality of plate nodes, the method further comprising:
biasing one or more plate nodes of the first domain, wherein writing logic states of the plurality of logic states to the first subset of the plurality of memory cells is based at least in part on biasing the one or more plate nodes of the first domain; and
biasing one or more plate nodes of the second domain, wherein writing logic states of the plurality of logic states to the second subset of the plurality of memory cells is based at least in part on biasing the one or more plate nodes of the second domain.
7 . The method of claim 2 , wherein coupling the plurality of storage elements with the plurality of memory cells is performed via a plurality of access lines that bypass the signal development cache with the plurality of memory cells.
8 . The method of claim 5 , wherein:
storing the respective cache signal for each of the plurality of logic states to the respective storage element is associated with a first latency; and
writing the plurality of logic states to the plurality of memory cells is associated with a second latency that is greater than the first latency.
9 . The method of claim 5 , wherein:
each of the plurality of memory cells comprises a material operable to store a logic state in a configurable material property; and
each of the plurality of storage elements is operable to store an electrical charge.
10 . The method of claim 5 , wherein:
each of the plurality of memory cells comprises a ferroelectric capacitor; and
each of the plurality of storage elements comprises a linear capacitor.
11 . The method of claim 2 , further comprising:
receiving a write command comprising the plurality of logic states, wherein the determining is based at least in part on the write command.
12 . The method of claim 2 , wherein writing the plurality of logic states to the plurality of memory cells is associated with a write-back operation.
13 . An apparatus, comprising:
a memory array comprising a plurality of memory cells;
a signal development cache comprising a plurality of cache elements different than the plurality of memory cells;
a sense amplifier array comprising a plurality of sense amplifiers; and
a controller operable to:
determine to store a respective cache signal, for each of a plurality of logic states for writing to the plurality of memory cells, at a respective one of the plurality of cache elements;
couple, based at least in part on the determination, the plurality of sense amplifiers with the plurality of cache elements to store the respective cache signal for each of the plurality of logic states to the respective cache element;
couple, after storing the respective cache signal for each of the plurality of logic states to the respective cache element, the plurality of cache elements with the plurality of memory cells; and
write the plurality of logic states to the plurality of memory cells based at least in part on coupling the plurality of cache elements with the plurality of memory cells.
14 . The apparatus of claim 13 , wherein, to store the respective cache signals for each of the plurality of logic states to the respective cache elements, the controller is operable to:
couple, during a first time interval, a first sense amplifier of the sense amplifier array with a first cache element of the plurality of cache elements; and
couple, during second time interval that follows the first time interval, the first sense amplifier of the sense amplifier array with a second cache element of the plurality of cache elements.
15 . The apparatus of claim 14 , wherein, to couple the plurality of cache elements with the plurality of memory cells, the controller is operable to:
couple, during a third time interval, the first cache element of the plurality of cache elements with a first memory cell of the plurality of memory cells; and
couple, during a fourth time interval that overlaps the third time interval, the second cache element of the plurality of cache elements with a second memory cell of the plurality of memory cells.
16 . The apparatus of claim 13 , wherein the memory array comprises a plurality of domains each associated with a respective subset of a plurality of word lines, and wherein the controller is operable to:
activate a word line of a first domain of the plurality of domains to couple a first subset of the plurality of memory cells with a first subset of the plurality of cache elements; and
activate a word line of a second domain of the plurality of domains to couple a second subset of the plurality of memory cells with a second subset of the plurality of cache elements.
17 . The apparatus of claim 16 , wherein each of the plurality of domains is associated with one or more of a plurality of plate nodes that are each operable to be biased independent of other plate nodes of the plurality of plate nodes, and wherein the controller is operable to:
bias one or more plate nodes of the first domain, wherein writing logic states of the plurality of logic states to the first subset of the plurality of memory cells is based at least in part on biasing the one or more plate nodes of the first domain; and
bias one or more plate nodes of the second domain, wherein writing logic states of the plurality of logic states to the second subset of the plurality of memory cells is based at least in part on biasing the one or more plate nodes of the second domain.
18 . The apparatus of claim 13 , further comprising a plurality of access lines that bypass the signal development cache, wherein coupling of the plurality of cache elements with the plurality of memory cells is performed via the plurality of access lines.
19 . The apparatus of claim 13 , wherein:
each of the plurality of memory cells comprises a material operable to store a logic state in a configurable material property; and
each of the plurality of cache elements is operable to store an electrical charge.
20 . The apparatus of claim 13 , wherein:
each of the plurality of memory cells comprises a ferroelectric capacitor; and
each of the plurality of cache elements comprises a linear capacitor.
21 . The apparatus of claim 13 , wherein the controller is operable to:
receive a write command comprising the plurality of logic states; and
perform the determination based at least in part on the write command.