PHOTONIC COMMUNICATION PLATFORM AND RELATED ARCHITECTURES, SYSTEMS AND METHODS
Photonic interposers that enable low-power, high-bandwidth inter-chip (e.g., board-level and/or rack-level) as well as intra-chip communication are described. Described herein are techniques, architectures and processes that improve upon the performance of conventional computers. Some embodiments provide photonic interposers that use photonic tiles, where each tile includes programmable photonic circuits that can be programmed based on the needs of a particular computer architecture. Some tiles are instantiations of a common template tile that are stitched together in a 1D or a 2D arrangement. Some embodiments described herein provide a programmable physical network designed to connect pairs of tiles together with photonic links.
1 . A photonic interposer comprising:
a plurality of photonics tiles that are instantiations of a template photonic tile, the plurality of photonic tiles including first, second, third and fourth photonic tiles, each of the plurality of photonics tiles comprising:
a first transceiver; and
electrical connections, coupled to the first transceiver, configured to permit electrical communication between the first transceiver and an electronic chip when the electronic chip is attached to the photonic interposer in correspondence with the photonic tile;
first and second bus waveguides each traversing the first and second photonic tiles;
third and fourth bus waveguides each traversing the third and fourth photonic tiles; and
first and second fibers, wherein:
the first fiber, the first bus waveguide and the fourth bus waveguide place the first transceiver of the first photonic tile in optical communication with the first transceiver of the fourth photonic tile, and
the second fiber, the second bus waveguide and the third bus waveguide place the first transceiver of the second photonic tile in optical communication with the first transceiver of the third photonic tile.
2 . The photonic interposer of claim 1 , wherein each of the plurality of photonics tiles further comprises a second transceiver, wherein the second transceiver of the first photonic tile is in optical communication with the second transceiver of the second photonic tile.
3 . The photonic interposer of claim 2 , wherein the second transceiver of the third photonic tile is in optical communication with the second transceiver of the fourth photonic tile.
4 . The photonic interposer of claim 1 , further comprising a third fiber, wherein the third fiber, the first bus waveguide and the fourth bus waveguide place the first transceiver of the first photonic tile in further optical communication with the first transceiver of the fourth photonic tile.
5 . The photonic interposer of claim 4 , wherein the first fiber, the third fiber, the first bus waveguide, the fourth bus waveguide, the first transceiver of the first photonic tile and the first transceiver of the fourth photonic tile form a closed loop.
6 . The photonic interposer of claim 4 , further comprising a fourth fiber, wherein the fourth fiber, the second bus waveguide and the third bus waveguide place the first transceiver of the second photonic tile in further optical communication with the first transceiver of the third photonic tile.
7 . The photonic interposer of claim 6 , wherein the second fiber, the fourth fiber, the second bus waveguide, the third bus waveguide, the first transceiver of the second photonic tile and the first transceiver of the third photonic tile form a closed loop.
8 . The photonic interposer of claim 1 , wherein each of the plurality of photonics tiles further comprises:
a polarization splitter coupled to both the first transceiver; and
a fiber coupler coupled to the polarization splitter.
9 . The photonic interposer of claim 1 , wherein the plurality of photonics tiles are arranged two-dimensionally, wherein the first and second photonic tiles form a first row of photonic tiles and the third and fourth photonic tiles form a second row of photonic tiles.
10 . The photonic interposer of claim 1 , wherein each of the plurality of photonics tiles is 24.8 mm×32 mm in size.
11 . A computing system comprising the photonic interposer of claim 1 and a first application-specific integrated circuit (ASIC) mounted on the photonic interposer, wherein the first ASIC comprises a first serializer-deserializer (SerDes) coupled to the first transceiver of the first photonic tile and a second SerDes coupled to the first transceiver of the second photonic tile
12 . The computing system of claim 11 , further comprising a plurality of through silicon vias (TSV) coupling the first SerDes with the first transceiver of the first photonic tile.
13 . The computing system of claim 11 , wherein the first ASIC comprises a Universal Chiplet Interconnect Express (UCIe) interface coupled to the first SerDes and configured to permit communication between the first ASIC and a second ASIC.
14 . The computing system of claim 11 , wherein the second ASIC is mounted on the photonic interposer.
15 . A method of assembling a package, comprising:
obtaining a photonic interposer comprising:
a plurality of photonics tiles that are instantiations of a template photonic tile, the plurality of photonic tiles including first, second, third and fourth photonic tiles, each of the plurality of photonics tiles comprising a first transceiver;
first and second bus waveguides each traversing the first and second photonic tiles; and
third and fourth bus waveguides each traversing the third and fourth photonic tiles;
attaching a first fiber to the first and fourth photonic tiles such that the first fiber, the first bus waveguide and the fourth bus waveguide place the first transceiver of the first photonic tile in optical communication with the first transceiver of the fourth photonic tile; and
attaching a second fiber to the second and third photonic tiles such that the second fiber, the second bus waveguide and the third bus waveguide place the first transceiver of the second photonic tile in optical communication with the first transceiver of the third photonic tile.
16 . The method of claim 15 , wherein each of the plurality of photonics tiles further comprises a second transceiver, wherein the second transceiver of the first photonic tile is in optical communication with the second transceiver of the second photonic tile.
17 . The method of claim 16 , wherein the second transceiver of the third photonic tile is in optical communication with the second transceiver of the fourth photonic tile.
18 . The method of claim 15 , further comprising:
attaching a third fiber to the photonic interposer such that the third fiber, the first bus waveguide and the fourth bus waveguide place the first transceiver of the first photonic tile in further optical communication with the first transceiver of the fourth photonic tile.
19 . The method of claim 18 , wherein the first fiber, the third fiber, the first bus waveguide, the fourth bus waveguide, the first transceiver of the first photonic tile and the first transceiver of the fourth photonic tile form a closed loop.
20 . The method of claim 18 , further comprising:
attaching a fourth fiber to the photonic interposer, wherein the fourth fiber, the second bus waveguide and the third bus waveguide place the first transceiver of the second photonic tile in further optical communication with the first transceiver of the third photonic tile.