PHOTONIC COMMUNICATION PLATFORM AND RELATED ARCHITECTURES, SYSTEMS AND METHODS
Photonic interposers that enable low-power, high-bandwidth inter-chip (e.g., board-level and/or rack-level) as well as intra-chip communication are described. Described herein are techniques, architectures and processes that improve upon the performance of conventional computers. Some embodiments provide photonic interposers that use photonic tiles, where each tile includes programmable photonic circuits that can be programmed based on the needs of a particular computer architecture. Some tiles are instantiations of a common template tile that are stitched together in a 1D or a 2D arrangement. Some embodiments described herein provide a programmable physical network designed to connect pairs of tiles together with photonic links.
1 . A computing system comprising:
a photonic interposer comprising a plurality of photonics tiles that are instantiations of a template photonic tile,
first and second application-specific integrated circuits (ASICs) mounted on the photonic interposer, wherein the first ASIC is coupled with a first photonic tile of the plurality of photonic tiles and the second ASIC is coupled with a second photonic tile of the plurality of photonic tiles; and
a data path placing the first ASIC in communication with the second ASIC, the data path comprising:
a first die-to-die (D2D) interface, embedded with the first ASIC, comprising a plurality of wires;
a first plurality of SerDes coupled to the plurality of wires;
a plurality of optical modulators, coupled with the first plurality of SerDes, formed in the first photonic tile;
a plurality of optical detectors, coupled with the plurality of optical modulators, formed in the second photonic tile;
a second plurality of SerDes coupled to the plurality of optical detectors; and
a second D2D interface, embedded with the second ASIC.
2 . The computing system of claim 1 , wherein the plurality of optical detectors are coupled with the plurality of optical modulators via waveguides formed on the photonic interposer.
3 . The computing system of claim 1 , wherein the plurality of optical detectors are coupled with the plurality of optical modulators via fibers.
4 . The computing system of claim 1 , wherein the first and second D2D interfaces comprise Advanced Interface Bus (AIB) interfaces.
5 . The computing system of claim 1 , wherein the first and second D2D interfaces comprise Universal Chiplet Interconnect Express (UCIe) interfaces.
6 . The computing system of claim 1 , wherein the data path spans a length greater than 2.5 cm from the first D2D interface to the second D2D interface.
7 . The computing system of claim 1 , wherein the data path further comprises:
a wavelength division multiplexer, formed in the first photonic tile, coupled to the plurality of optical modulators; and
a wavelength division demultiplexer, formed in the second photonic tile, coupled to the plurality of optical detectors.
8 . The computing system of claim 1 , wherein the data path further comprises:
a first polarization splitter, formed in the first photonic tile, coupled to the plurality of optical modulators; and
a second polarization splitter, formed in the second photonic tile, coupled to the plurality of optical detectors.
9 . The computing system of claim 1 , further comprising a further data path placing the first ASIC in communication with the second ASIC, the further data path comprising:
a third plurality of SerDes coupled to the plurality of wires;
a further plurality of optical modulators, coupled with the third plurality of SerDes, formed in the second photonic tile;
a further plurality of optical detectors, coupled with the further plurality of optical modulators, formed in the first photonic tile; and
a fourth plurality of SerDes coupled to the further plurality of optical detectors.
10 . The computing system of claim 9 , wherein the further data path permits communication from the second D2D interface to the first D2D interface.
11 . The computing system of claim 1 , wherein each of the plurality of photonics tiles is 24.8 mm×32 mm in size.
12 . The computing system of claim 1 , wherein the plurality of photonics tiles are stitched together in a 2D arrangement defining a plurality of rows of photonic tiles.
13 . A computing system comprising:
a photonic interposer comprising a plurality of optical transceivers,
an application-specific integrated circuits (ASIC) coupled to the photonic interposer and comprising a die-to-die (D2D) interface; and
a data path coupling the D2D interface to the plurality of optical transceivers, the data path comprising a plurality of SerDes.
14 . The computing system of claim 13 , wherein the ASIC is mounted on the photonic interposer.
15 . The computing system of claim 13 , wherein the photonic interposer comprises a plurality of photonics tiles that are instantiations of a template photonic tile, wherein the data path couples the D2D interface to optical transceivers defined in a first photonic tile of the plurality of photonic tiles.
16 . The computing system of claim 15 , wherein each of the plurality of photonics tiles is 24.8 mm×32 mm in size.
17 . The computing system of claim 13 , wherein the D2D interface comprises an Advanced Interface Bus (AIB) interface.
18 . The computing system of claim 13 , wherein the D2D interface comprises a Universal Chiplet Interconnect Express (UCIe) interface.
19 . The computing system of claim 13 , wherein the photonic interposer comprises a wavelength division multiplexer coupled to the plurality of optical transceivers.
20 . The computing system of claim 13 , wherein the photonic interposer comprises a polarization splitter coupled to the plurality of optical transceivers.