FIXED-SIZE IMAGE ALPHA CHANNEL COMPRESSION TECHNIQUES

1 . A method for fixed size texture compression utilizing dynamic alpha channel compression, comprising:

determining a first endpoint of a pixel block including four pixels, each pixel represented by a plurality of channels;

determining a second endpoint of the pixel block, which is not the first endpoint;

encoding the first endpoint and the second endpoint using a first plurality of bits, wherein the first endpoint and the second endpoint are encoded using a total of 31 bits;

encoding a first quantization level using a second plurality of bits;

encoding a second quantization level using a third plurality of bits;

encoding an alpha map of the four pixels using a fourth plurality of bits;

encoding a location of the first endpoint and a location of the second endpoint using a fifth plurality of bits; and

storing an addressing indicator bit based on a distance between a value of the first endpoint and a value of the second endpoint.

2 . The method of claim 1 , further comprising:

detecting a number of visible pixels;

encoding an alpha map using a first portion of the fourth plurality of bits; and

encoding an average alpha value using a second portion of the fourth plurality of bits.

3 . The method of claim 2 , wherein the first portion of the fourth plurality of bits is 4 bits, and the fourth plurality of bits is 8 bits.

4 . The method of claim 2 , wherein the first portion of the fourth plurality of bits is configured to store a value which corresponds to one of twelve alpha maps, each alpha map distinct from another alpha map.

5 . The method of claim 2 , further comprising:

detecting that all four pixels are visible; and

encoding an alpha indicator using a third portion of the fourth plurality of bits; and

encoding an average alpha value using a fourth portion of the fourth plurality of bits, which is larger than the second portion of the fourth plurality of bits.

6 . The method of claim 5 , wherein the fourth portion of the fourth plurality of bits is 6 bits.

7 . The method of claim 1 , further comprising:

storing the first endpoint utilizing a first encoding in response to determining that the addressing indicator bit has a first binary value.

8 . The method of claim 7 , further comprising:

storing the first endpoint utilizing a second encoding in response to determining that the addressing indicator bit has a second binary value.

9 . The method of claim 1 , further comprising:

determining a visibility threshold for the pixel block; and

selecting the alpha map based on the visibility threshold.

10 . A non-transitory computer-readable medium storing a set of instructions for fixed size texture compression utilizing dynamic alpha channel compression, the set of instructions comprising:

one or more instructions that, when executed by one or more processing circuitries of a device, cause the device to:

determine a first endpoint of a pixel block including four pixels, each pixel represented by a plurality of channels;

determine a second endpoint of the pixel block, which is not the first endpoint;

encode the first endpoint and the second endpoint using a first plurality of bits, wherein the first endpoint and the second endpoint are encoded using a total of 31 bits;

encode a first quantization level using a second plurality of bits;

encode a second quantization level using a third plurality of bits;

encode an alpha map of the four pixels using a fourth plurality of bits;

encode a location of the first endpoint and a location of the second endpoint using a fifth plurality of bits; and

store an addressing indicator bit based on a distance between a value of the first endpoint and a value of the second endpoint.

11 . A system for fixed size texture compression utilizing dynamic alpha channel compression comprising:

a processing circuitry;

a memory, the memory containing instructions that, when executed by the processing circuitry, configure the system to:

determine a first endpoint of a pixel block including four pixels, each pixel represented by a plurality of channels;

determine a second endpoint of the pixel block, which is not the first endpoint;

encode the first endpoint and the second endpoint using a first plurality of bits, wherein the first endpoint and the second endpoint are encoded using a total of 31 bits;

encode a first quantization level using a second plurality of bits;

encode a second quantization level using a third plurality of bits;

encode an alpha map of the four pixels using a fourth plurality of bits;

encode a location of the first endpoint and a location of the second endpoint using a fifth plurality of bits; and

store an addressing indicator bit based on a distance between a value of the first endpoint and a value of the second endpoint.

12 . The system of claim 11 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:

detect a number of visible pixels;

encode an alpha map using a first portion of the fourth plurality of bits; and

encode an average alpha value using a second portion of the fourth plurality of bits.

13 . The system of claim 12 , wherein the first portion of the fourth plurality of bits is 4 bits, and the fourth plurality of bits is 8 bits.

14 . The system of claim 12 , wherein the first portion of the fourth plurality of bits is configured to store a value which corresponds to one of twelve alpha maps, each alpha map distinct from another alpha map.

15 . The system of claim 12 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:

detect that all four pixels are visible; and

encode an alpha indicator using a third portion of the fourth plurality of bits; and

encode an average alpha value using a fourth portion of the fourth plurality of bits, which is larger than the second portion of the fourth plurality of bits.

16 . The system of claim 15 , wherein the fourth portion of the fourth plurality of bits is 6 bits.

17 . The system of claim 11 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:

store the first endpoint utilizing a first encoding in response to determining that the addressing indicator bit has a first binary value.

18 . The system of claim 17 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:

store the first endpoint utilizing a second encoding in response to determining that the addressing indicator bit has a second binary value.

19 . The system of claim 11 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:

determine a visibility threshold for the pixel block; and

select the alpha map based on the visibility threshold.