SYSTEM AND METHOD FOR MEMORY BANDWIDTH REDUCTION USING A PROGRAMMABLE CACHE LINE
A system and method for memory bandwidth reduction utilized a programmable cache line. The method includes generating an instruction to render a modified texture based on a modification of a texture, the texture stored as a plurality of lines in a memory, each line addressable by a unique address; determining an amount of data to read from a first line of a texture based on the modification; configuring a programmable cache line to read into a cache at least the determined amount of data from a unique address corresponding to the first line; and storing at least a portion of the determined amount of data in a first line of a framebuffer.
1 . A method for memory bandwidth reduction using a programmable cache line, comprising:
generating an instruction to render a modified texture based on a preexisting texture, the preexisting texture stored as a plurality of lines in a memory;
selecting an amount of data to read from a first line of a texture based on the modification;
configuring a programmable cache line to read into a cache at least the selected amount of data from a unique address of the memory corresponding to the first line; and
storing at least a portion of the selected amount of data in a first line of a framebuffer.
2 . The method of claim 1 , further comprising:
selecting an amount of data to read from a second line of the preexisting texture;
configuring the programmable cache line to read at least the selected amount of data from a unique address of the memory corresponding to the second line; and
storing at least a portion of the selected amount of data in the first line of the framebuffer after the amount of data read from the first line of the texture.
3 . The method of claim 1 , wherein configuring the programmable cache line to read a predetermined amount of data further comprises:
writing a predetermined value to an indicator bit, wherein the predetermined value corresponds to a predetermined amount of data.
4 . The method of claim 3 , wherein configuring the programmable cache line to read a determined second amount of data further comprises:
writing a second predetermined value to the indicator bit, which is different from the predetermined value.
5 . The method of claim 3 , further comprising:
configuring the programmable cache line to read the predetermined amount of data from a memory address.
6 . The method of claim 5 , further comprising:
writing a predetermined value corresponding to the memory address to a second indicator bit, wherein the second indicator bit indicates an address from an address space of the memory.
7 . The method of claim 1 , further comprising:
determining an amount of data to read from a first line of a second texture map which is equal to the determined amount of data to read from the first line of the texture map, wherein the second texture map is a bitmap representing a channel of the texture map.
8 . The method of claim 1 , further comprising:
rendering the modified texture to include any one of: a rotation, a stretch, a contraction, a reflection, a scaling, and a combination thereof.
9 . The method of claim 1 , wherein the amount of data is a discrete amount of bits.
10 . The method of claim 1 , further comprising:
reading data from the framebuffer; and
configuring a display to display an image based on the data read from the framebuffer.
11 . A non-transitory computer-readable medium storing a set of instructions for memory bandwidth reduction using a programmable cache line, the set of instructions comprising:
one or more instructions that, when executed by one or more processors of a device, cause the device to:
generate an instruction to render a modified texture based on a preexisting texture, the preexisting texture stored as a plurality of lines in a memory;
select an amount of data to read from a first line of a texture based on the modification;
configure a programmable cache line to read into a cache at least the selected amount of data from a unique address of the memory corresponding to the first line; and
store at least a portion of the selected amount of data in a first line of a framebuffer.
12 . A system for memory bandwidth reduction using a programmable cache line comprising:
a processing circuitry;
a memory, the memory containing instructions that, when executed by the processing circuitry, configure the system to:
generate an instruction to render a modified texture based on a preexisting texture, the preexisting texture stored as a plurality of lines in a memory;
select an amount of data to read from a first line of a texture based on the modification;
configure a programmable cache line to read into a cache at least the selected amount of data from a unique address of the memory corresponding to the first line; and
store at least a portion of the selected amount of data in a first line of a framebuffer.
13 . The system of claim 12 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:
select an amount of data to read from a second line of the preexisting texture;
configure the programmable cache line to read at least the selected amount of data from a unique address of the memory corresponding to the second line; and
store at least a portion of the selected amount of data in the first line of the framebuffer after the amount of data read from the first line of the texture.
14 . The system of claim 12 , wherein the memory contains further instructions that, when executed by the processing circuitry for configuring the programmable cache line to read a predetermined amount of data, further configure the system to:
write a predetermined value to an indicator bit, wherein the predetermined value corresponds to a predetermined amount of data.
15 . The system of claim 14 , wherein the memory contains further instructions that, when executed by the processing circuitry for configuring the programmable cache line to read a determined second amount of data, further configure the system to:
write a second predetermined value to the indicator bit, which is different from the predetermined value.
16 . The system of claim 14 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:
configure the programmable cache line to read the predetermined amount of data from a memory address.
17 . The system of claim 16 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:
write a predetermined value corresponding to the memory address to a second indicator bit, wherein the second indicator bit indicates an address from an address space of the memory.
18 . The system of claim 12 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:
determine an amount of data to read from a first line of a second texture map which is equal to the determined amount of data to read from the first line of the texture map, wherein the second texture map is a bitmap representing a channel of the texture map.
19 . The system of claim 12 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:
render the modified texture to include any one of:
a rotation, a stretch, a contraction, a reflection, a scaling, and a combination thereof.
20 . The system of claim 12 , wherein the amount of data is a discrete amount of bits.
21 . The system of claim 12 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:
read data from the framebuffer; and
configure a display to display an image based on the data read from the framebuffer.