IP Library Patent Application 19360581
Patent Application
App. No. 19/360,581

FIXED-SIZE BLOCK COMPRESSION TECHNIQUES FOR RGB CHANNELS

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Quick Facts
Patent No.
US None
App. No.
19/360,581
Abstract

A system and method for fixed size texture compression using a selected encoding scheme is presented. The method includes determining a first endpoint of a four-pixel block, each pixel represented by a red, green, and blue channel; determining a second endpoint of the pixel block; determining a distance between the first endpoint and the second endpoint; selecting an encoding scheme based on a determined distance; encoding the first endpoint and the second endpoint using a first plurality of bits based on the selected encoding scheme; encoding a first quantization level using a second plurality of bits based on the selected encoding scheme; encoding a second quantization level using a third plurality of bits based on the selected encoding scheme; and encoding a location of the first endpoint and a location of the second endpoint using a fourth plurality of bits based on the selected encoding scheme.

Claims (68)

1 . A method for fixed size texture compression using a selected encoding scheme, comprising:

determining a first endpoint of a pixel block including four pixels, each pixel represented by a red channel, a green channel and a blue channel;

determining a second endpoint of the pixel block;

determining a distance between a value of the first endpoint and a value of the second endpoint;

selecting an encoding scheme of a plurality of encoding schemes based on a determined distance;

encoding the first endpoint and the second endpoint using a first plurality of bits based on the selected encoding scheme;

encoding a first quantization level using a second plurality of bits based on the selected encoding scheme;

encoding a second quantization level using a third plurality of bits based on the selected encoding scheme; and

encoding a location of the first endpoint and a location of the second endpoint using a fourth plurality of bits based on the selected encoding scheme.

2 . The method of claim 1 , further comprising:

selecting the encoding scheme to encode the first endpoint and the second endpoint using an absolute value encoding scheme.

3 . The method of claim 1 , further comprising:

selecting the encoding scheme to encode the first endpoint and the second endpoint using an offset encoding scheme.

4 . The method of claim 3 , further comprising:

encoding the first endpoint using a group of bits of the first plurality of bits; and

encoding the second endpoint such that each value of a channel of the second endpoint is encoded relative to a value of a corresponding channel of the first endpoint.

5 . The method of claim 1 , further comprising:

encoding the pixel block further to include an indicator, wherein the indicator indicates an identifier of the encoding scheme of the plurality of encoding schemes.

6 . The method of claim 1 , further comprising:

encoding the red channel using a first encoding scheme of the plurality of encoding schemes.

7 . The method of claim 6 , further comprising:

encoding any one of: the blue channel or the green channel, using a second encoding scheme of the plurality of encoding schemes.

8 . The method of claim 1 , further comprising:

encoding a green channel of the first endpoint using a first portion of the first plurality of bits;

encoding a red channel of the first endpoint using a second portion of the first plurality of bits; and

encoding a blue channel of the first endpoint using a third portion of the first plurality of bits, wherein a number of bits of the first portion is greater than a number of bits of each of the second portion and the third portion.

9 . The method of claim 1 , further comprising:

encoding a pixel layout of the pixel block.

10 . A non-transitory computer-readable medium storing a set of instructions for fixed size texture compression using a selected encoding scheme, the set of instructions comprising:

one or more instructions that, when executed by one or more processing circuitries of a device, cause the device to:

determine a first endpoint of a pixel block including four pixels, each pixel represented by a red channel, a green channel and a blue channel;

determine a second endpoint of the pixel block;

determine a distance between a value of the first endpoint and a value of the second endpoint;

select an encoding scheme of a plurality of encoding schemes based on a determined distance;

encode the first endpoint and the second endpoint using a first plurality of bits based on the selected encoding scheme;

encode a first quantization level using a second plurality of bits based on the selected encoding scheme;

encode a second quantization level using a third plurality of bits based on the selected encoding scheme; and

encode a location of the first endpoint and a location of the second endpoint using a fourth plurality of bits based on the selected encoding scheme.

11 . A system for fixed size texture compression using a selected encoding scheme comprising:

one or more processing circuitries configured to:

determine a first endpoint of a pixel block including four pixels, each pixel represented by a red channel, a green channel and a blue channel;

determine a second endpoint of the pixel block;

determine a distance between a value of the first endpoint and a value of the second endpoint;

select an encoding scheme of a plurality of encoding schemes based on a determined distance;

encode the first endpoint and the second endpoint using a first plurality of bits based on the selected encoding scheme;

encode a first quantization level using a second plurality of bits based on the selected encoding scheme;

encode a second quantization level using a third plurality of bits based on the selected encoding scheme; and

encode a location of the first endpoint and a location of the second endpoint using a fourth plurality of bits based on the selected encoding scheme.

12 . The system of claim 11 , wherein the one or more processing circuitries are further configured to:

select the encoding scheme to encode the first endpoint and the second endpoint using an absolute value encoding scheme.

13 . The system of claim 11 , wherein the one or more processing circuitries are further configured to:

select the encoding scheme to encode the first endpoint and the second endpoint using an offset encoding scheme.

14 . The system of claim 13 , wherein the one or more processing circuitries are further configured to:

encode the first endpoint using a group of bits of the first plurality of bits; and

encode the second endpoint such that each value of a channel of the second endpoint is encoded relative to a value of a corresponding channel of the first endpoint.

15 . The system of claim 11 , wherein the one or more processing circuitries are further configured to:

encode the pixel block further to include an indicator, wherein the indicator indicates an identifier of the encoding scheme of the plurality of encoding schemes.

16 . The system of claim 11 , wherein the one or more processing circuitries are further configured to:

encode the red channel using a first encoding scheme of the plurality of encoding schemes.

17 . The system of claim 16 , wherein the one or more processing circuitries are further configured to:

encode any one of: the blue channel or the green channel, use a second encoding scheme of the plurality of encoding schemes.

18 . The system of claim 11 , wherein the one or more processing circuitries are further configured to:

encode a green channel of the first endpoint using a first portion of the first plurality of bits;

encode a red channel of the first endpoint using a second portion of the first plurality of bits; and

encode a blue channel of the first endpoint using a third portion of the first plurality of bits, wherein a number of bits of the first portion is greater than a number of bits of each of the second portion and the third portion.

19 . The system of claim 11 , wherein the one or more processing circuitries are further configured to:

encode a pixel layout of the pixel block; and

encode a pixel layout of the pixel block.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 9, 2026
From: THINK SILICON SINGLE MEMBER P.C. AND APPLIED MATERIALS, INC.
To: QUALCOMM INCORPORATED
Reel/Frame 075735/0803 →
CHANGE OF NAME Recorded Mar 6, 2026
From: THINK SILICON RESEARCH AND TECHNOLOGY SINGLE MEMBER S.A.
To: THINK SILICON SINGLE MEMBER P.C.
Reel/Frame 075032/0035 →