IP Library Patent Application 19362023
Patent Application
App. No. 19/362,023

TECHNIQUES FOR OPTIMIZING NEURAL NETWORKS FOR MEMOIZATION USING SHIFTED VALUE LOCALIZATION

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Patent No.
US None
App. No.
19/362,023
Abstract

A system and method for dynamically adjusting value similarity thresholds to increase cache hits in a value cache utilizing memoization is presented. The method includes: receiving an input matrix comprising a plurality of values; selecting a portion of the input matrix; generating a similarity threshold based on a determined number of least significant bits (LSBs) for comparing a first value of the portion to a second value of the portion; determining that the first and second values are identical in all but the determined number of LSBs; adjusting the first value based on the second value in response to determining that the first value and the second value are within the similarity threshold; generating a new input matrix based on the adjusted first value; and processing the new input matrix with a convolutional neural network (CNN), wherein dynamically adjusting the number of LSBs cache hits in the value cache.

Claims (65)

1 . A method for dynamically adjusting value similarity thresholds to increase cache hits in a value cache utilizing memoization, comprising:

receiving an input matrix comprising a plurality of values;

selecting a portion of the input matrix;

generating a similarity threshold based on a determined number of least significant bits (LSBs) for comparing a first value of the portion to a second value of the portion;

determining that the first value and the second value are identical in all but the determined number of LSBs;

adjusting the first value based on the second value in response to determining that the first value and the second value are within the similarity threshold;

generating a new input matrix based on the adjusted first value; and

processing the new input matrix with a convolutional neural network (CNN), wherein dynamically adjusting the number of LSBs cache hits in the value cache.

2 . The method of claim 1 , further comprising:

increasing the number of LSBs when a cache hit rate exceeds a predefined threshold.

3 . The method of claim 1 , further comprising:

decreasing the number of LSBs when a cache miss rate exceeds a predefined threshold.

4 . The method of claim 1 , wherein adjusting the first value based on the second value further comprises:

replacing the first value with an average of the first value and the second value.

5 . The method of claim 4 , further comprising:

selecting a nearest integer value to the average value; and

replacing the first value with the nearest integer value.

6 . The method of claim 1 , further comprising:

performing a z-buffer test on the portion of the input matrix to determine the similarity threshold.

7 . The method of claim 1 , further comprising:

processing the new input matrix with a convolutional operation using a kernel of the CNN.

8 . The method of claim 1 , further comprising

adjusting a plurality of weights of the CNN such that a first weight value is adjusted based on proximity to a neighboring weight value.

9 . The method of claim 1 , further comprising:

dynamically adjusting the number of LSBs based on an execution parameter.

10 . The method of claim 9 , wherein the execution parameter includes any one of: a number of processing iterations, a time period, a number of cache accesses, and any combination thereof.

11 . A non-transitory computer-readable medium storing a set of instructions for dynamically adjusting value similarity thresholds to increase cache hits in a value cache utilizing memoization, the set of instructions comprising:

one or more instructions that, when executed by one or more processing circuitries of a device, cause the device to:

receive an input matrix comprising a plurality of values;

select a portion of the input matrix;

generate a similarity threshold based on a determined number of least significant bits (LSBs) for comparing a first value of the portion to a second value of the portion;

determine that the first value and the second value are identical in all but the determined number of LSBs;

adjust the first value based on the second value in response to determining that the first value and the second value are within the similarity threshold;

generate a new input matrix based on the adjusted first value; and

process the new input matrix with a convolutional neural network (CNN), wherein dynamically adjusting the number of LSBs cache hits in the value cache.

12 . A system for dynamically adjusting value similarity thresholds to increase cache hits in a value cache utilizing memoization comprising:

a processing circuitry;

a memory, the memory containing instructions that, when executed by the processing circuitry, configure the system to:

receive an input matrix comprising a plurality of values;

select a portion of the input matrix;

generate a similarity threshold based on a determined number of least significant bits (LSBs) for comparing a first value of the portion to a second value of the portion;

determine that the first value and the second value are identical in all but the determined number of LSBs;

adjust the first value based on the second value in response to determining that the first value and the second value are within the similarity threshold;

generate a new input matrix based on the adjusted first value; and

process the new input matrix with a convolutional neural network (CNN), wherein dynamically adjusting the number of LSBs cache hits in the value cache.

13 . The system of claim 12 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:

increase the number of LSBs when a cache hit rate exceeds a predefined threshold.

14 . The system of claim 12 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:

decrease the number of LSBs when a cache miss rate exceeds a predefined threshold.

15 . The system of claim 12 , wherein the memory contains further instructions that, when executed by the processing circuitry for adjusting the first value based on the second value, further configure the system to:

replace the first value with an average of the first value and the second value.

16 . The system of claim 15 , wherein the memory contains further instructions which

when executed by the processing circuitry further configure the system to:

select a nearest integer value to the average value; and

replace the first value with the nearest integer value.

17 . The system of claim 12 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:

perform a z-buffer test on the portion of the input matrix to determine the similarity threshold.

18 . The system of claim 12 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:

process the new input matrix with a convolutional operation using a kernel of the CNN.

19 . The system of claim 12 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:

adjust a plurality of weights of the CNN such that a first weight value is adjusted based on proximity to a neighboring weight value.

20 . The system of claim 12 , wherein the memory contains further instructions which when executed by the processing circuitry further configure the system to:

dynamically adjust the number of LSBs based on an execution parameter.

21 . The system of claim 20 , wherein the execution parameter includes any one of:

a number of processing iterations, a time period, a number of cache accesses, and any combination thereof.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 9, 2026
From: THINK SILICON SINGLE MEMBER P.C. AND APPLIED MATERIALS, INC.
To: QUALCOMM INCORPORATED
Reel/Frame 075735/0803 →
CHANGE OF NAME Recorded Mar 6, 2026
From: THINK SILICON RESEARCH AND TECHNOLOGY SINGLE MEMBER S.A.
To: THINK SILICON SINGLE MEMBER P.C.
Reel/Frame 075032/0035 →