3D NAND - HIGH ASPECT RATIO STRINGS AND CHANNELS
Aspects of the disclosure relate to forming a completed stack of layers. Forming the completed stack of layers may include forming a first stack of layers on a first substrate and forming a second stack of layers on a second substrate. The first stack of layers may be bonded to the second stack of layers. The first or second substrate may be removed. Prior to bonding the first stack of layers and the second stack of layer, one or more holes may be etched in the first stack of layers. After removing the second substrate, one or more holes may be etched in the second stack of layers, wherein each of the one or more holes in the second stack of layers extend into a corresponding hole in the one or more holes in the first stack of layers.
1 - 17 . (canceled)
18 . A method of forming a memory cell stack in 3D NAND memory, the method comprising:
forming a first stack of layers on a first logic layer;
etching a first hole in the first stack of layers from a side of the first stack of layers opposite the logic layer;
forming a second stack of layers on the side of the first stack of layers opposite the logic layer; and
etching a second hole in the second stack of layers, wherein the second hole aligns with first hole to form an extended hole.
19 . The method of claim 18 , wherein forming the second stack of layers on the side of the first stack of layers opposite the logic layer comprises depositing the second stack of layers on the side of the first stack of layers opposite the logic layer.
20 . The method of claim 19 , further comprising depositing a conductive material in the extended hole to form a contact.
21 . The method of claim 19 , further comprising depositing a plurality of conformal layers in the extended hole to at least partially form one or more memory cells of the memory cell stack.
22 . The method of claim 19 , further comprising depositing a dielectric material in the extended hole to form a support pillar.
23 . The method of claim 19 , further comprising:
filling the first hole with a sacrificial material before depositing the second stack of layers; and
removing the sacrificial material from the first hole after the second hole is etched.
24 . The method of claim 19 , further comprising depositing a buffer layer on the first stack of layers before depositing the second stack of layers.
25 . The method of claim 19 , further comprising prior to depositing the second stack of layers, sequentially depositing a plurality of conformal layers in the first hole to at least partially form memory cells of the memory cell stack.
26 . The method of claim 25 , wherein at least partially forming memory cells further comprises depositing silicon oxide in the first hole to form a dielectric core after sequentially depositing the plurality of conformal layers.
27 . The method of claim 19 , wherein the first stack of layers and the second stack of layers each comprise alternating layers of silicon nitride and silicon oxide or alternating layers of silicon oxide and polysilicon.
28 . The method of claim 18 , wherein:
forming the second stack of layers on the side of the first stack of layers opposite the logic layer comprises bonding the second stack of layers to the side of the first stack of layers opposite the logic layer; and
the second stack of layers is directly bonded to the first stack of layers without using an intervening adhesive.
29 . The method of claim 28 , wherein the second stack of layers are attached to a carrier substrate when the second stack of layers are bonded to the first stack of layers.
30 . The method of claim 29 , further comprising removing the carrier substrate prior to etching the second hole the second stack of layers.
31 . The method of claim 30 , further comprising depositing a conductive material in the extended hole to form a contact.
32 . The method of claim 30 , further comprising depositing a plurality of conformal layers in the extended hole to at least partially form one or more memory cells of the memory cell stack.
33 . The method of claim 30 , further comprising depositing a dielectric material in the extended hole to form a support pillar.
34 . The method of claim 30 , further comprising:
filling the first hole with a sacrificial material before bonding the second stack of layers to the side of the first stack of layers; and
removing the sacrificial material from the first hole after the second hole is etched.
35 . The method of claim 30 , further comprising depositing a buffer layer on the first stack of layers before bonding the second stack of layers to the side of the first stack of layers.
36 . The method of claim 30 , further comprising prior to bonding the second stack of layers to the side of the first stack of layers, sequentially depositing a plurality of conformal layers in the first hole to at least partially form memory cells of the memory cell stack.
37 . The method of claim 36 , wherein at least partially forming memory cells further comprises depositing silicon oxide in the first hole to form a dielectric core after sequentially depositing the plurality of conformal layers.
38 . The method of claim 30 , wherein the first stack of layers and the second stack of layers each comprise alternating layers of silicon nitride and silicon oxide or alternating layers of silicon oxide and polysilicon.