METHODS FOR PERFORMING MULTIPLE MEMORY OPERATIONS IN RESPONSE TO A SINGLE COMMAND AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME
Memory devices, memory systems, and methods of operating memory devices and systems are disclosed in which a single command can trigger a memory device to perform multiple operations, such as a single refresh command that triggers the memory device to both perform a refresh command and to perform a mode register read. One such memory device comprises a memory, a mode register, and circuitry configured, in response to receiving a command to perform a refresh operation at the memory, to perform the refresh operation at the memory, and to perform a read of the mode register. The memory can be a first memory portion, the memory device can comprise a second memory portion, and the circuitry can be further configured, in response to the command, to provide on-die termination at the second memory portion of the memory system during at least a portion of the read of the mode register.
1 . A host system, comprising:
circuitry configured to:
transmit, within a first duration, a first command associated with performing a first operation at a first memory portion of a memory system; and
transmit, within the first duration, a second command associated with performing a second operation of a different kind than the first operation at the first memory portion of the memory system.
2 . The host system of claim 1 , wherein the first operation comprises a refresh operation and the second operation comprises a mode register read operation.
3 . The host system of claim 1 , wherein the circuitry is further configured to:
transmit the first command during a first clock cycle; and
transmit the second command during a second clock cycle that is a next consecutive clock cycle after the first clock cycle, wherein the first duration comprises the first clock cycle and the second clock cycle.
4 . The host system of claim 3 , wherein the circuitry is further configured to:
transmit the second command during the second clock cycle and a third clock cycle that is a next consecutive clock cycle after the second clock cycle, the first duration comprising the first clock cycle, the second clock cycle, and the third clock cycle.
5 . The host system of claim 3 , wherein the first command and the second command are each transmitted via a command/address bus.
6 . The host system of claim 1 , wherein the circuitry is further configured to:
receive, during a second duration, data from a mode register of the memory system.
7 . The host system of claim 6 , wherein the circuitry is further configured to:
transmit, via a second chip select terminal, signaling comprising an indication for a second memory portion to provide on-die termination during at least a portion of the second duration.
8 . The host system of claim 6 , wherein the data comprises information corresponding to a temperature of the first memory portion.
9 . The host system of claim 6 , wherein the data comprises information corresponding to a refresh rate of the first memory portion.
10 . The host system of claim 1 , wherein the circuitry is further configured to:
transmit, via a first chip select terminal, signaling comprising an indication to perform the first command and the second command at the first memory portion.
11 . The host system of claim 1 , wherein the first command comprises a refresh command and the second command comprises a mode register read command.
12 . A method, comprising:
transmitting, within a first duration, a first command associated with performing a first operation at a first memory portion of a memory system; and
transmitting, within the first duration, a second command associated with performing a second operation of a different kind than the first operation at the first memory portion of the memory system.
13 . The method of claim 12 , wherein the first operation comprises a refresh operation and the second operation comprises a mode register read operation.
14 . The method of claim 12 , further comprising:
transmitting the first command during a first clock cycle; and
transmitting the second command during a second clock cycle that is a next consecutive clock cycle after the first clock cycle, wherein the first duration comprises the first clock cycle and the second clock cycle.
15 . The method of claim 14 , further comprising:
transmitting the second command during the second clock cycle and a third clock cycle that is a next consecutive clock cycle after the second clock cycle, the first duration comprising the first clock cycle, the second clock cycle, and the third clock cycle.
16 . The method of claim 14 , wherein the first command and the second command are each transmitted via a command/address bus.
17 . The method of claim 12 , further comprising:
receiving, during a second duration, data from a mode register of the memory system.
18 . The method of claim 17 , further comprising:
transmitting, via a second chip select terminal, signaling comprising an indication for a second memory portion to provide on-die termination during at least a portion of the second duration.
19 . The method of claim 17 , wherein the data comprises information corresponding to a temperature of the first memory portion.
20 . A non-transitory computer-readable medium storing code comprising instructions which, when executed by processing circuitry of a host system, cause the host system to:
transmit, within a first duration, a first command associated with performing a first operation at a first memory portion of a memory system; and
transmit, within the first duration, a second command associated with performing a second operation of a different kind than the first operation at the first memory portion of the memory system.