MULTI-STAGE ERASE OPERATION OF MEMORY CELLS IN A MEMORY SUB-SYSTEM
Control logic in a memory device relocates a set of valid data from a first subset of memory blocks to a second subset of memory blocks. A first erase sub-operation of a multi-stage erase operation to place the first subset of memory blocks in a first erase state. In response to a request to execute a programming operation, executing a second erase sub-operation of the multi-stage erase operation to place the first subset of memory blocks in a second erase state. The programming operation is executed to program the first subset of memory blocks.
1 . A memory device comprising:
a memory array comprising a plurality of memory cells; and
control logic, operatively coupled with the memory array, to perform operations comprising:
relocating a set of valid data from a first subset of memory blocks to a second subset of memory blocks;
executing a first erase sub-operation of a multi-stage erase operation to place the first subset of memory blocks in a first erase state;
in response to a request to execute a programming operation, executing a second erase sub-operation of the multi-stage erase operation to place the first subset of memory blocks in a second erase state; and
executing the programming operation to program the first subset of memory blocks.
2 . The memory device of claim 1 , wherein the first erase sub-operation is executed in response to a command to erase the first subset of memory blocks.
3 . The memory device of claim 1 , wherein the first erase sub-operation comprises applying a first erase pulse having a first erase voltage level to memory cells of the first subset of memory blocks.
4 . The memory device of claim 3 , wherein the second erase sub-operation comprises applying a second erase pulse having a second erase voltage level to memory cells of the first subset of memory blocks.
5 . The memory device of claim 4 , wherein the second erase voltage level is higher than the first erase voltage level.
6 . The memory device of claim 1 , wherein the first erase state corresponds to a first threshold voltage level and the second erase state corresponds to a second threshold voltage level, and wherein the first threshold voltage level is higher than the second threshold voltage level.
7 . The memory device of claim 1 , wherein relocating the set of valid data comprises executing a garbage collection operation that identifies the first subset of memory blocks as available for erasing.
8 . A memory device comprising:
a memory array comprising a set of memory cells; and
control logic, operatively coupled with the memory array, to perform operations comprising:
identifying a first subset of memory blocks to be erased;
executing a first erase sub-operation of a multi-stage erase operation to erase the first subset of memory blocks to a first threshold voltage level, wherein the first erase sub-operation comprises applying, to the first subset of memory blocks, a first erase pulse having a first erase voltage level; and
executing a second erase sub-operation of the multi-stage erase operation to erase the first subset of memory blocks to a second threshold voltage level, wherein the second erase sub-operation comprises applying, to the first subset of memory blocks, a second erase pulse having a second erase voltage level, and wherein the first erase voltage level of the first erase sub-operation is lower than the second erase voltage level of the second erase sub-operation.
9 . The memory device of claim 8 , wherein the operations further comprise executing a garbage collection operation to relocate a set of valid data of the first subset of memory blocks to a second subset of memory blocks prior to executing the first erase sub-operation.
10 . The memory device of claim 8 , the operations further comprising executing a programming operation to program the first subset of memory blocks following execution of the second erase sub-operation.
11 . The memory device of claim 8 , wherein the first erase sub-operation is executed in response to a command to erase the first subset of memory blocks.
12 . The memory device of claim 11 , wherein the second erase sub-operation is executed in response to a command to program the first subset of memory blocks.
13 . The memory device of claim 8 , wherein the first erase sub-operation comprises a pre-program operation.
14 . A memory device comprising:
a memory array comprising a plurality of memory blocks; and
control logic, operatively coupled with the memory array, to perform operations comprising:
executing a scatter-gather process to identify valid data stored in a first set of memory blocks and relocate the valid data to one or more destination memory blocks;
executing a first erase sub-operation of a multi-stage erase operation on the first set of memory blocks; and
executing a second erase sub-operation of the multi-stage erase operation on the first set of memory blocks.
15 . The memory device of claim 14 , wherein the scatter-gather process comprises identifying the first set of memory blocks to be erased.
16 . The memory device of claim 15 , wherein the scatter-gather process comprises denoting the first set of memory blocks with a flag.
17 . The memory device of claim 16 , wherein the first erase sub-operation comprises identifying the flag corresponding to the first set of memory blocks.
18 . The memory device of claim 15 , wherein the operations further comprise identifying a request to execute a program operation.
19 . The memory device of claim 18 , wherein the second erase sub-operation is executed in response to the request to execute the program operation.
20 . The memory device of claim 14 , wherein the first erase sub-operation comprises applying a first erase pulse having a first erase voltage level to the first set of memory blocks, and wherein the second erase sub-operation comprises applying a second erase pulse having a second erase voltage level to first set of memory blocks.