IP Library Patent Application 19414889
Patent Application
App. No. 19/414,889

KERNEL BYPASS FOR ISCSI AND NVME/TCP APPLICATIONS

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Quick Facts
Patent No.
US None
App. No.
19/414,889
Abstract

Techniques for host devices to offload iSCSI and NVMe/TCP data plane processing for data plane traffic to a NIC, and for the NIC to perform the data plane traffic processing in hardware. Traditionally, network protocol stacks have been implemented within the kernel of an operating system of a computing device. In light of this, iSCSI and NVMe/TCP user space applications running on host devices interact with a kernel of an operating system using system calls in order to send network traffic. However, the system calls, TCP/IP processing, and data copying required when communicating via the kernel increases CPU utilization as well as I/O latency. Techniques described herein include configuring the host device to enable kernel bypass for data path traffic for iSCSI and NVMe/TCP user space applications, and a NIC may include hardware configured to perform the iSCSI and NVMe/TCP processing for iSCSI and NVMe/TCP connections.

Claims (35)

1 . A network interface card (NIC), comprising:

a communications interface configured to communicatively couple the NIC to a host device;

a transmit queue configured to receive iSCSI or NVMe/TCP protocol data unit (PDU) transmit work requests directly from an application running in a user space of the host device, wherein the PDU transmit work requests are written into transmit queue memory mapped in a virtual address space of the application;

one or more hardware chips encoded with an iSCSI protocol stack, an NVMe/TCP protocol stack, and a TCP/IP protocol stack configured to process the PDU transmit work requests to generate packets for transmission;

a network interface configured to transmit the packets over a network and receive packets from a destination device; and

a receive queue configured to receive PDU completions and provide the application with direct access to PDU header and data buffers.

2 . The NIC of claim 1 , further comprising a virtual memory registration module configured to register transmit and receive virtual memory buffers with the NIC.

3 . The NIC of claim 2 , wherein the virtual memory registration module is implemented in hardware within the one or more hardware chips.

4 . The NIC of claim 1 , further comprising a zero copy transmit module configured to transmit data directly from user space application buffers without copying data to kernel buffers.

5 . The NIC of claim 4 , wherein the zero copy transmit module is encoded in hardware within the one or more hardware chips.

6 . The NIC of claim 1 , further comprising a direct data placement module configured to place received data directly into user space application buffers.

7 . The NIC of claim 6 , wherein the direct data placement module bypasses kernel space when placing the received data into the user space application buffers.

8 . The NIC of claim 1 , wherein the receive queue is configured to provide notifications to a kernel space of the host device indicating that PDU completions have been received.

9 . The NIC of claim 1 , wherein the communications interface comprises a Peripheral Component Interconnect Express interface.

10 . The NIC of claim 1 , wherein the one or more hardware chips are configured to perform TCP segmentation offload and TCP reassembly operations for the packets.

11 . A method for kernel bypass in data path processing for iSCSI and NVMe/TCP applications, the method comprising:

establishing, by a kernel space of a host device, an iSCSI or NVMe/TCP connection with a destination device;

creating a transmit queue and mapping transmit queue memory in an application's virtual address space;

creating a receive queue and mapping receive queue memory in the application's virtual address space;

writing, by an application running in a user space of the host device, iSCSI or NVMe/TCP PDU transmit work requests directly into the transmit queue memory, wherein the PDU transmit work requests bypass the kernel space; and

retrieving, by the application, PDU receive completions from the receive queue memory, wherein the PDU receive completions are retrieved via a data path that bypasses the kernel space.

12 . The method of claim 11 , further comprising registering transmit and receive virtual memory buffers with a network interface card prior to establishing the iSCSI or NVMe/TCP connection.

13 . The method of claim 12 , wherein the registering is performed through system calls from the application to the kernel space.

14 . The method of claim 11 , further comprising polling, by the application, the receive queue to determine whether PDU receive completions have been written by a network interface card.

15 . The method of claim 14 , wherein the polling is performed directly from the user space without kernel space involvement.

16 . The method of claim 11 , wherein the PDU transmit work requests are processed by hardware-implemented iSCSI and NVMe/TCP protocol stacks within a network interface card to generate packets for transmission to the destination device.

17 . A system for offloading iSCSI and NVMe/TCP data plane processing comprising:

a host device having a user space and a kernel space, wherein an iSCSI or NVMe/TCP application executes in the user space;

a network interface card (NIC) communicatively coupled to the host device and comprising hardware-implemented protocol stacks for iSCSI, NVMe/TCP, and TCP/IP processing;

a virtual memory registration module configured to register transmit and receive virtual memory buffers with the NIC;

a zero copy transmit module configured to transmit data directly from user space application buffers; and

a direct data placement module configured to place received data directly into the user space application buffers, wherein data plane traffic flows directly between the user space application and the NIC without passing through the kernel space.

18 . The system of claim 17 , wherein the host device comprises one or more processors and memory, and the NIC is communicatively coupled to the host device via a Peripheral Component Interconnect Express interface.

19 . The system of claim 18 , wherein the virtual memory registration module, zero copy transmit module, and direct data placement module are implemented in hardware within one or more hardware chips of the NIC.

20 . The system of claim 19 , wherein the hardware-implemented protocol stacks are configured to perform TCP segmentation offload, TCP reassembly operations, and iSCSI or NVMe/TCP header and data digest computation and validation.

Assignments (1)
CHANGE OF NAME Recorded May 5, 2026
From: CHELSIO COMMUNICATIONS, INC.
To: SPEEDNIC LLC
Reel/Frame 075561/0001 →