Apparatus for Persistent Memory Management
Apparatuses, systems, methods, and computer program products are disclosed for persistent memory management. Persistent memory management may include replicating a persistent data structure in volatile memory buffers of at least two non-volatile storage devices. Persistent memory management may include preserving a snapshot copy of data in association with completion of a barrier operation for the data. Persistent memory management may include determining which interface of a plurality of supported interfaces is to be used to flush data from a processor complex.
1 . An apparatus comprising:
means for determining which of a memory interface and a peripheral interface is to be used to flush data from a processor complex;
means for issuing a memory serializing instruction that flushes the data from the processor complex using the memory interface in response to determining that the memory interface is to be used to flush the data; and
means for issuing a peripheral serializing instruction that flushes the data from the processor complex using the peripheral interface in response to determining that the peripheral interface is to be used to flush the data.
2 . The apparatus of claim 1 , wherein one or more of the means for determining, the means for issuing a memory serializing instruction, and the means for issuing a peripheral serializing instruction comprise at least a portion of a device driver executing on a host computing device, the device driver supporting both the memory interface and the peripheral interface.
3 . The apparatus of claim 1 , wherein the memory interface comprises a host memory bus interface and the peripheral interface comprises a peripheral component interconnect express (PCIe) interface.
4 . The apparatus of claim 1 , further comprising means for determining completion of a serializing instruction.
5 . The apparatus of claim 1 , further comprising:
a hardware controller for one or more volatile memory buffers each associated with a non-volatile storage medium of a plurality of non-volatile storage mediums, the hardware controller configured to: create a copy of data of a first ACM buffer in response to determining completion of a barrier operation, wherein the creating comprises storing the copy in a second ACM buffer of a second volatile memory buffer of a second non-volatile storage medium of the plurality of non-volatile storage mediums.
6 . The apparatus of claim 5 , wherein the copy is stored on a blank page of the second ACM buffer.
7 . The apparatus of claim 6 , wherein the hardware controller is further configured to write data of the first ACM buffer to a first non-volatile storage medium.
8 . The apparatus of claim 7 , wherein the hardware controller is further configured to provide the data of the first ACM buffer to a client from the first non-volatile storage medium after recovery from a restart event.
9 . The apparatus of claim 8 , wherein the hardware controller is further configured to provide the data of the first ACM buffer by loading the data from the first non-volatile storage medium into a first volatile memory buffer.
10 . The apparatus of claim 5 , wherein the hardware controller is further configured to receive a barrier request for a first volatile memory buffer.
11 . The apparatus of claim 1 , further comprising:
means for creating a copy of data of a first ACM buffer in response to determining completion of a barrier operation, wherein the creating comprises storing the copy in a second ACM buffer of a second volatile memory buffer of a second non-volatile storage device.
12 . The apparatus of claim 11 , wherein the copy is stored on a blank page of the second ACM buffer.
13 . The apparatus of claim 1 , further comprising a controller configured to:
determine completion of a barrier operation for a first auto-commit memory (ACM) buffer of a first volatile memory buffer of a first non-volatile storage device;
create a copy of data of the first ACM buffer in response to determining completion of the barrier operation, wherein the creating comprises storing the copy in a second ACM buffer of a second volatile memory buffer of a second non-volatile storage device;
dynamically switch data operations for the data of the first ACM buffer to the copy;
receive an updated version of the data of the first ACM buffer, wherein the updated version is inconsistent with the copy; and
synchronize, in response to a trigger associated with the first ACM buffer, the updated version of the data to the first ACM buffer and the copy, wherein the updated version of the data of the first ACM buffer is accessible to both an application for the first non-volatile storage device and an application for the second non-volatile storage device.
14 . The apparatus of claim 13 , wherein the copy is stored on a blank page of the second ACM buffer.
15 . The apparatus of claim 13 , further comprising providing the data of the first ACM buffer to a client from the first non-volatile storage device after recovery from a restart event.
16 . The apparatus of claim 15 , further comprising providing the data by loading the data from the first non-volatile storage device into the first volatile memory buffer.
17 . The apparatus of claim 13 , further comprising receiving a barrier request for the first volatile memory buffer.
18 . An apparatus, comprising:
means for determining which of a memory interface and a peripheral interface is to be used to flush data from a processor complex;
means for issuing a memory serializing instruction that flushes the data from the processor complex using the memory interface in response to determining that the memory interface is to be used to flush the data; and
means for issuing a peripheral serializing instruction that flushes the data from the processor complex using the peripheral interface in response to determining that the peripheral interface is to be used to flush the data, wherein one or more of the means for determining, the means for issuing a memory serializing instruction, and the means for issuing a peripheral serializing instruction comprise at least a portion of a device driver executing on a host computing device, the device driver supporting both the memory interface and the peripheral interface, wherein the memory interface comprises a host memory bus interface and the peripheral interface comprises a peripheral component interconnect express (PCIe) interface.
19 . The apparatus of claim 18 , further comprising means for determining completion of a serializing instruction.
20 . An apparatus, comprising:
means for determining which of a memory interface and a peripheral interface is to be used to flush data from a processor complex;
means for issuing a memory serializing instruction that flushes the data from the processor complex using the memory interface in response to determining that the memory interface is to be used to flush the data;
means for issuing a peripheral serializing instruction that flushes the data from the processor complex using the peripheral interface in response to determining that the peripheral interface is to be used to flush the data, wherein the memory interface comprises a host memory bus interface and the peripheral interface comprises a peripheral component interconnect express (PCIe) interface; and
means for determining completion of a serializing instruction.