IP Library › Patent Application 60297940
Patent Application Provisional
App. No. 60/297,940 · Confirmation No. 4888

Low power clock distribution methodology using on-chip transmission lines

Inventor: Hidetaka Magoshi
Provisional Application Expired
⬇ PDF
 Code Description Pages PDF
2001-06-13 TRNA Transmittal of New Application 1 View
2001-06-13 SPEC Specification 6 View
2001-06-13 CLM Claims 1 View
2001-06-13 DRW Drawings-only black and white line drawings 3 View
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this application's details
Quick Facts
App. No.
60/297,940
Filed
2001-06-13