IP Library › Patent Application 61768265
Patent Application Provisional
App. No. 61/768,265 · Confirmation No. 8189

Scalable, Low Latency, Deep Buffered Switch Architecture

Provisional Application Expired
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 Code Description Pages PDF
2013-07-08 APP.FILE.REC Filing Receipt 3 View
2013-06-20 R48.REQ Request under Rule 48 correcting inventorship 2 View
2013-06-20 ADS Application Data Sheet 7 View
2013-06-20 CFILE Request for Corrected Filing Receipt 5 View
2013-06-20 WFEE Fee Worksheet (SB06) 2 View
2013-06-20 N417 Electronic Filing System Acknowledgment Receipt 3 View
2013-06-20 TRAN.LET Transmittal Letter 1 View
2013-04-11 APP.FILE.REC Filing Receipt 3 View
2013-04-05 WFEE Fee Worksheet (SB06) 2 View
2013-04-02 CFILE Request for Corrected Filing Receipt 5 View
2013-04-02 ADS Application Data Sheet 7 View
2013-04-02 N417 Electronic Filing System Acknowledgment Receipt 2 View
2013-03-13 APP.FILE.REC Filing Receipt 3 View
2013-02-22 TR.PROV Provisional Cover Sheet (SB16) 1 View
2013-02-22 ADS Application Data Sheet 7 View
2013-02-22 SPEC Specification 10 View
2013-02-22 CLM Claims 2 View
2013-02-22 ABST Abstract 1 View
2013-02-22 DRW.NONBW Drawings-other than black and white line drawings 5 View
2013-02-22 WFEE Fee Worksheet (SB06) 2 View
2013-02-22 N417 Electronic Filing System Acknowledgment Receipt 3 View
2013-02-22 SCORE Placeholder sheet indicating presence of supplemental content in Supplemental Complex Repository for Examiners(SCORE) 1 View
0001-01-03 DRW.SUPP Drawings-black and white line and/or other drawings — View
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Quick Facts
App. No.
61/768,265
Filed
2013-02-22