Method for the programming of an anti-fuse, and associated programming circuit

1. A method for programming an anti-fuse transistor comprising a drain, a source and a well connected together, and a gate, the method comprising:

applying a reference potential to the gate of the anti-fuse transistor; and

applying a high potential greater than the reference potential to the drain of the anti-fuse transistor.

2. A method according to claim 1 , wherein a first access transistor is connected to the anti-fuse transistor, the first access transistor comprising a drain connected to the source of the anti-fuse transistor and a source for receiving the high potential; and wherein applying the high potential comprises turning on the first access transistor.

3. A method according to claim 1 , wherein a second access transistor is connected to the anti-fuse transistor, the second access transistor comprising a drain connected to the gate of the anti-fuse transistor and a source for receiving the reference potential; and wherein applying the reference potential comprises turning on the second access transistor.

4. A method according to claim 1 , wherein a a first current source and a third access transistor are connected to the anti-fuse transistor, the first current source having a first terminal connected to the gate of the anti-fuse transistor and a second terminal for receiving a power supply potential, the third access transistor comprising a drain connected to the source of the anti-fuse transistor and a source for receiving the reference potential and a gate; and further comprising determining a programming state of the anti-fuse transistor by applying a read signal to the gate of the third access transistor.

5. A method according to claim 1 , wherein a second current source and a fourth access transistor are connected to the anti-fuse transistor, the fourth access transistor comprising a source connected to the source of the anti-fuse transistor and a drain and a gate, the second current source having a first terminal connected to the drain of the fourth access transistor and a second terminal for receiving a power supply potential; and further comprising determining a programming state of the anti-fuse transistor by applying a read signal to the gate of the fourth access transistor.

6. A method according to claim 1 , wherein a third current source, a fifth access transistor and a sixth access transistor are connected to the anti-fuse transistor, the fifth access transistor comprising a drain connected to the source of the anti-fuse transistor and a source and a gate, the third current source having a first terminal connected to the source of the fifth access transistor and a second terminal for receiving the reference potential, and the sixth access transistor comprising a source connected to the gate of the anti-fuse transistor and a drain for receiving a power supply potential and a gate; and further comprising determining a programming state of the anti-fuse transistor by applying a read signal to the gates of the fifth and sixth access transistors.

7. A method according to claim 1 , wherein a fourth current source, a seventh access transistor and an eighth access transistor are connected to the anti-fuse transistor, the seventh access transistor comprising a drain connected to the gate of the anti-fuse transistor and a source and a gate, the fourth current source having a first terminal connected to the source of the seventh access transistor and a second terminal for receiving the reference potential, and an eighth access transistor comprising a source connected to the source of the anti-fuse transistor and a drain for receiving a power supply potential; and further comprising determining a programing state of the anti-fuse transistor by applying a read signal to the gates of the seventh and eighth access transistors.

8. A method for programming an anti-fuse transistor comprising a first conduction terminal, a second conduction terminal and a well connected together, and a control terminal, the method comprising:

determining a programming state of the anti-fuse transistor, and if the anti-fuse transistor has not been programmed, then

applying a reference potential to the control terminal of the anti-fuse transistor, and

applying a high potential greater than the reference potential to the first conduction terminal of the anti-fuse transistor.

9. A method according to claim 8 , wherein the anti-fuse transistor comprises a MOSFET, and wherein the first conduction terminal defines a drain, the second conduction terminal defines a source and the control terminal defines a gate of the MOSFET.

10. A method according to claim 8 , wherein a first access transistor is connected to the anti-fuse transistor, the first access transistor comprising a first conduction terminal connected to the second conduction terminal of the anti-fuse transistor and a second conduction terminal for receiving the high potential; and wherein applying the high potential comprises turning on the first access transistor.

11. A method according to claim 8 , wherein a second access transistor is connected to the anti-fuse transistor, the second access transistor comprising a first conduction terminal connected to the control terminal of the anti-fuse transistor and a second conduction terminal for receiving the reference potential; and wherein applying the reference potential comprises turning on the second access transistor.

12. A method according to claim 8 , wherein a a first current source and a third access transistor are connected to the anti-fuse transistor, the first current source having a first terminal connected to the control terminal of the anti-fuse transistor and a second terminal for receiving a power supply potential, the third access transistor comprising a first conduction terminal connected to the second conduction terminal of the anti-fuse transistor and a second conduction terminal for receiving the reference potential and a control terminal; and wherein determining the programming state of the anti-fuse transistor comprises applying a read signal to the control terminal of the third access transistor.

13. A method according to claim 8 , wherein a second current source and a fourth access transistor are connected to the anti-fuse transistor, the fourth access transistor comprising a second conduction terminal connected to the second conduction terminal of the anti-fuse transistor and a first conduction terminal and a control terminal, and the second current source having a first terminal connected to the first conduction terminal of the fourth access transistor, and a second terminal for receiving a power supply potential; and wherein determining the programming state of the anti-fuse transistor comprises applying a read signal to the control terminal of the fourth access transistor.

14. A method according to claim 8 , wherein a third current source, a fifth access transistor and a sixth access transistor are connected to the anti-fuse transistor, the fifth access transistor comprising a first conduction terminal connected to the second conduction terminal of the anti-fuse transistor and a second conduction terminal and a control terminal, the third current source having a first terminal connected to the second conduction terminal of the fifth access transistor and a second terminal for receiving the reference potential, and the sixth access transistor comprising a second conduction terminal connected to the control terminal of the anti-fuse transistor and a first conduction terminal for receiving a power supply potential and a control terminal; and wherein determining the programming state of the anti-fuse transistor comprises applying a read signal to the control terminals of the fifth and sixth access transistors.

15. A method according to claim 8 , wherein a fourth current source, a seventh access transistor and an eighth access transistor are connected to the anti-fuse transistor, the seventh access transistor comprising a first conduction terminal connected to the control terminal of the anti-fuse transistor and a second conduction terminal and a control terminal, the fourth current source having a first terminal connected to the second conduction terminal of the seventh access transistor and a second terminal for receiving the reference potential, and an eighth access transistor comprising a second conduction terminal connected to the second conduction terminal of the anti-fuse transistor and a first conduction terminal for receiving a power supply potential; and wherein determining the programming state of the anti-fuse transistor comprises applying a read signal to the control terminals of the seventh and eighth access transistors.

16. A circuit comprising:

an anti-fuse transistor comprising a drain, a source and a well connected together, and a gate; and

a programming circuit connected to said anti-fuse transistor for applying a reference potential to the gate of said anti-fuse transistor, and for applying a high potential greater than the reference potential to the drain of said anti-fuse transistor.

17. A circuit according to claim 16 , wherein said programming circuit comprises a first access transistor connected to the anti-fuse transistor, said first access transistor comprising a drain connected to the source of said anti-fuse transistor and a source for receiving the high potential; and wherein said programming circuit applies the high potential by turning on said first access transistor.

18. A circuit according to claim 16 , wherein said programming circuit comprises a second access transistor comprising a drain connected to the gate of said anti-fuse transistor and a source for receiving the reference potential; and wherein said programming circuit applies the reference potential by turning on said second access transistor.

19. A circuit according to claim 16 , further comprising a reading circuit connected to said anti-fuse transistor and comprising:

a first current source having a first terminal connected to the gate of said anti-fuse transistor, and a second terminal for receiving a power supply potential; and

a third access transistor comprising a drain connected to the source of said anti-fuse transistor, and a source for receiving the reference potential.

20. A circuit according to claim 16 , further comprising a reading circuit connected to said anti-fuse transistor and comprising:

a fourth access transistor comprising a source connected to the source of said anti-fuse transistor, and a drain; and

a second current source having a first terminal connected to the drain of said fourth access transistor, and a second terminal for receiving a power supply potential.

21. A circuit according to claim 16 , further comprising a reading circuit connected to said anti-fuse transistor and comprising:

a fifth access transistor comprising a drain connected to the source of said anti-fuse transistor;

a third current source having a first terminal connected to the source of said fifth access transistor, and a second terminal for receiving the reference potential; and

a sixth access transistor comprising a source connected to the gate of said anti-fuse transistor, and a drain for receiving a power supply potential.

22. A circuit according to claim 16 , further comprising a reading circuit connected to said anti-fuse transistor and comprising:

a seventh access transistor comprising a drain connected to the gate of said anti-fuse transistor, and a source;

a fourth current source having a first terminal connected to the source of said seventh access transistor, and a second terminal for receiving the reference potential; and

an eighth access transistor comprising a source connected to the source of said anti-fuse transistor, and a drain for receiving a power supply potential.