Method and apparatus for a low-density parity-check decoder

1. A low-density parity-check (LDPC) decoder, comprising:

a memory; and

a processor programmed to:

initialize the LDPC decoder;

calculate a probability for each check node;

calculate a probability for each bit node;

calculate soft decisions;

update the bit nodes according to the calculated soft decisions;

calculate values from the calculated soft decisions;

perform a parity check on the calculated values;

update log-likelihood ratios (LLRs) if a bit error is detected in the calculated values;

update the bit nodes according to the updated LLRs; and

repeat the foregoing post initialization steps.

2. The LDPC decoder of claim 1 , wherein the initialization step the processor is programmed to:

initialize a plurality of bit nodes with log-likelihood ratios (LLRs);

initialize a plurality of check nodes to a predetermined setting;

associate each bit node to one or more corresponding check nodes; and

associate each check node to one or more corresponding bit nodes.

3. The LDPC decoder of claim 1 , wherein the processor is programmed to update the LLRs according to initial and intermediate LLRs adjusted by first and second factors.

4. The LDPC decoder of claim 1 , wherein the processor is programmed to:

repeat the foregoing post initialization steps if a bit error is detected and the number of iterations of said steps is less than a first preset value; and

update the LLRs and the bit nodes according to the updated LLRs, and repeat the foregoing post initialization steps if a bit error is detected and the number of iterations of said steps is greater than or equal to the first preset value.

5. The LDPC decoder of claim 4 , wherein the processor is programmed to cease further processing if a bit error is detected and the number of iterations exceeds a second preset value, the second preset value being greater than the first preset value.

6. The LDPC decoder of claim 1 , wherein the value is a ternary value, and wherein the processor is programmed to:

set the ternary value to one when the soft decision is greater than or equal to a threshold (M);

set the ternary value to negative one when the soft decision is less than negative M; and

set the ternary value to zero when the soft decision is less than M and greater negative M.

7. The LDPC decoder of claim 6 , wherein the processor is programmed to adaptively determine M as a scaled average magnitude of intermediate soft decisions.

8. The LDPC decoder of claim 6 , wherein the processor is programmed to reduce by 2 N a size of a set over which a distance minimization is calculated to update a portion of the LLRs if N of the ternary values associated with a symbol other than the LLRs under consideration have a non-zero value.

9. The LDPC decoder of claim 6 , wherein the processor is programmed to update a portion of the LLRs by subtraction without distance minimization if all the ternary values have a non-zero value.

10. The LDPC decoder of claim 6 , wherein the processor is programmed to apply a full size of a set over which a distance minimization is calculated to update a portion of the LLRs if all of the ternary values are zero.

11. A computer-readable storage medium, comprising computer instructions for:

initializing a plurality of bit nodes with log-likelihood ratios (LLRs);

initializing a plurality of check nodes to a predetermined setting;

associating each bit node to one or more corresponding check nodes;

associating each check node to one or more corresponding bit nodes;

calculating a probability for each check node;

calculating a probability for each bit node;

calculating soft decisions;

updating the bit nodes according to the calculated soft decisions;

calculating values according to a sign of the calculated soft decisions;

performing a parity check on the calculated values;

updating the LLRs according to initial and intermediate LLRs adjusted by first and second factors if a bit error is detected in the calculated values;

updating the bit nodes according to the updated LLRs; and

repeating the foregoing post initialization steps.

12. The storage medium of claim 11 , comprising computer instructions for:

repeating the foregoing post initialization steps if a bit error is detected and the number of iterations of said steps is less than a first preset value; and

updating the LLRs and the bit nodes according to the updated LLRs, and repeating the foregoing post initialization steps if a bit error is detected and the number of iterations of said steps is greater than or equal to the first preset value.

13. The storage medium of claim 12 , comprising computer instructions for ceasing further processing if a bit error is detected and the number of iterations exceeds a second preset value, the second preset value being greater than the first preset value.

14. The storage medium of claim 11 , wherein the value is a ternary value, and wherein the storage medium comprises computer instructions for:

setting the ternary value to one when the soft decision is greater than or equal to a threshold (M);

setting the ternary value to negative one when the soft decision is less than negative M;

setting the ternary value to zero when the soft decision is less than M and greater negative M; and

adaptively determine M as a scaled average magnitude of intermediate soft decisions.

15. The storage medium of claim 14 , comprising computer instructions for:

reducing by 2 N a size of a set over which a distance minimization is calculated to update a portion of the LLRs if N of the ternary values associated with a symbol other than the LLRs under consideration has a non-zero value;

updating a portion of the LLRs by subtraction without distance minimization if all the ternary values have a non-zero value; and

applying a full size of a set over which a distance minimization is calculated to update a portion of the LLRs if all of the ternary values are zero.

16. A base station, comprising:

a transceiver;

a memory; and

a processor programmed to:

intercept messages from a selective call radio; and

decode said messages by:

initializing a plurality of bit nodes with log-likelihood ratios (LLRs);

initializing a plurality of check nodes to a predetermined setting;

associating each bit node to one or more corresponding check nodes;

associating each check node to one or more corresponding bit nodes;

calculating a probability for each check node;

calculating a probability for each bit node;

calculating soft decisions according to corresponding check nodes and previous soft decisions of the bit nodes;

updating the bit nodes according to the calculated soft decisions;

calculating values according to a sign of the calculated soft decisions;

performing a parity check on the calculated values;

updating the LLRs if a bit error is detected in the calculated values;

updating the bit nodes according to the updated LLRs; and

repeating the foregoing post initialization steps.

17. The base station of claim 16 , wherein the processor is programmed to update the LLRs according to initial and intermediate LLRs adjusted by first and second factors.

18. The base station of claim 16 , wherein the processor is programmed to:

repeat the foregoing post initialization steps if a bit error is detected and the number of iterations of said steps is less than a first preset value;

update the LLRs and the bit nodes according to the updated LLRs, and repeat the foregoing post initialization steps if a bit error is detected and the number of iterations of said steps is greater than or equal to the first preset value; and

cease further processing if a bit error is detected and the number of iterations exceeds a second preset value, the second preset value being greater than the first preset value.

19. The base station of claim 16 , wherein the value is a ternary value, and wherein the processor is programmed to:

set the ternary value to one when the soft decision is greater than or equal to a threshold (M);

set the ternary value to negative one when the soft decision is less than negative M;

set the ternary value to zero when the soft decision is less than M and greater negative M; and

adaptively determine M as a scaled average magnitude of intermediate soft decisions.

20. The base station of claim 19 , wherein the processor is programmed to:

reducing by 2 N a size of a set over which a distance minimization is calculated to update a portion of the LLRs if N of the ternary bits associated with a symbol other than the LLRs under consideration has a non-zero value;

update a portion of the LLRs by subtraction without distance minimization if all the ternary values have a non-zero value;

apply a full size of a set over which a distance minimization is calculated to update a portion of the LLRs if all of the ternary values are zero.