Integrated circuit device, method of manufacturing the same and method of forming vanadium oxide film
View Patent ↗A vanadium oxide film is formed on an interlayer insulating layer, and a silicon oxide film and a silicon nitride film are formed on the vanadium oxide film in this order. With a resist pattern used as a mask, the silicon nitride film is patterned. Then, the resist pattern is removed using a stripping solution or oxygen plasma ashing. Next, with the patterned silicon nitride film used as a mask, the silicon oxide film and the vanadium oxide film are etched to form a resistor film of vanadium oxide.
1. An integrated circuit device comprising:
a resistor film connected between two wires and containing vanadium oxide;
a first film which is provided on said resistor film, formed in a same pattern as said resistor film as seen from a direction perpendicular to a top surface of said resistor film, and formed of a first material different from vanadium oxide; and
a second film which is provided on said first film, formed in a same pattern as said resistor film and said first film as seen from said direction perpendicular to said top surface of said resistor film, and formed of a second material different from vanadium oxide and said first material.
2. The integrated circuit device according to claim 1 , wherein said first material comprises an insulating material containing silicon.
3. The integrated circuit device according to claim 1 , wherein said second material comprises an insulating material containing silicon.
4. The integrated circuit device according to claim 1 , wherein said second material comprises a metal or an alloy.
5. The integrated circuit device according to claim 4 , wherein said second material is one metal selected from a group consisting of Al, Ti, Cu, Ta, W and Ni, or an alloy of said metal, or an alloy consisting essentially of two or more metals in said group.
6. The integrated circuit device according to claim 1 , further comprising:
a substrate;
a multi-layer wiring structure provided on said substrate; and
a logic circuit section provided at a top surface of said substrate and wiring layers located below a topmost layer of said multi-layer wiring structure, said resistor film being laid at said topmost layer of said multi-layer wiring structure.
7. A method of manufacturing an integrated circuit device, comprising:
forming an insulating film at whose top surface two wires are exposed on a substrate;
forming a film containing vanadium oxide on a region of said insulating film which includes wire-exposing portions at which said two wires are exposed;
forming a first film of a first material different from vanadium oxide on said film;
forming a second film of a second material different from vanadium oxide and said first material on said first film;
forming a resist film on said second film;
patterning said resist film in such a way that said resist film remains at a region including a region directly overlying said wire-exposing portions and a region where both two wires are connected;
selectively etching out said second film using said patterned resist film as a mask;
removing said patterned resist film; and
selectively etching out said first film and said film containing vanadium oxide using said etched second film as a mask.
8. The method according to claim 7 , wherein said removing of said patterned resist film comprises dissolving said resist film in a stripping solution.
9. The method according to claim 7 , wherein said removing of said patterned resist film comprises performing oxygen plasma ashing on said resist film.
10. The method according to claim 7 , wherein in said forming of said first film, said first material comprises an insulating material containing silicon.
11. The method according to claim 7 , wherein in said forming of said second film, said second material comprises an insulating material containing silicon.
12. The method according to claim 7 , wherein in said forming of said second film, said second material comprises a metal or an alloy.
13. The method according to claim 12 , wherein said second material is one metal selected from a group consisting of Al, Ti, Cu, Ta, W and Ni, or an alloy of said metal, or an alloy consisting essentially of two or more metals in said group.
14. A method of forming a vanadium oxide film, comprising:
forming a film containing vanadium oxide on a substrate;
forming a first film of a first material different from vanadium oxide on said film;
forming a second film of a second material different from vanadium oxide and said first material on said first film;
forming a resist film on said second film;
patterning said resist film;
selectively etching out said second film using said patterned resist film as a mask;
removing said patterned resist film; and
selectively etching out said first film and said film containing vanadium oxide using said etched second film as a mask.
15. The method according to claim 14 , wherein said removing of said patterned resist film comprises dissolving said resist film in a stripping solution.
16. The method according to claim 14 , wherein said removing of said patterned resist film comprises performing oxygen plasma ashing on said resist film.
17. The method according to claim 14 , wherein in said forming of said first film, said first material comprising an insulating material containing silicon.
18. The method according to claim 14 , wherein in said forming of said second film, said second material comprising an insulating material containing silicon.
19. The method according to claim 14 , wherein in said forming of said second film, said second material comprising a metal or an alloy.
20. The method according to claim 19 , wherein said second material is one metal selected from a group consisting of Al, Ti, Cu, Ta, W and Ni, or an alloy of said metal, or an alloy consisting essentially of two or more metals in said group.