High-speed receiver architecture

1. A receiver comprising:

an interleaved analog to digital converter (ADC) having multiple analog to digital converter (ADC) channels, wherein the interleaved ADC is based on a lookahead pipelined architecture using open-loop residue amplifiers in the pipeline; and

a multi-channel equalizer coupled to the interleaved ADC, the multi-channel equalizer capable of applying different equalization to the different ADC channels,

wherein the multi-channel equalizer has a same or higher degree of parallelism as the interleaved ADC, and

wherein the ADC channels are further demultiplexed before being received by the multi-channel equalizer.

2. The receiver of claim 1 wherein the multi-channel equalizer comprises:

a feedforward equalizer (FFE) coupled to a Viterbi decoder having a channel estimator.

3. The receiver of claim 2 wherein the FFE and/or the channel estimator for the Viterbi decoder are adapted on a sub-sampled basis using an LMS algorithm.

4. The receiver of claim 1 wherein the multi-channel equalizer applies an equalization that includes both a term based on shared coefficients for all ADC channels and another term based on channel-dependent coefficients.

5. A receiver comprising:

an interleaved analog to digital converter (ADC) having multiple analog to digital converter (ADC) channels, wherein the interleaved ADC is based on a lookahead pipelined architecture using open-loop residue amplifiers in the pipeline; and

a multi-channel equalizer coupled to the interleaved ADC, the multi-channel equalizer capable of applying different equalization to the different ADC channels.

6. A receiver comprising:

an interleaved analog to digital converter (ADC) having multiple analog to digital converter (ADC) channels;

a multi-channel equalizer coupled to the interleaved ADC, the multi-channel equalizer capable of applying different equalization to the different ADC channels; and

a timing recovery circuit coupled to receive an output of the interleaved ADC and an error signal from the multi-channel equalizer, for driving a clock for the interleaved ADC,

wherein the timing recovery circuit comprises a pulse preprocessor that adapts to a time-varying impulse response of a communications channel.

7. A transceiver chip for 10 G or higher fiber optic communication, comprising the following integrated on a single integrated circuit:

a host interface for receiving 10 G electrical digital data in a host format and for transmitting 10 G electrical digital data in a host format;

a laser driver port for generating an electrical signal modulated by 10 G data and suitable for driving a laser driver;

transmit path circuitry coupled between the host interface and the laser driver port;

a TIA port for receiving an electrical signal modulated by 10 G data from a transimpedance amplifier; and

receive path circuitry coupled between the TIA port and the host interface, the receive path circuitry comprising an interleaved analog to digital converter (ADC) having N analog to digital converter (ADC) channels for receiving the 10 G electrical signal from the TIA port, where N is an integer, the interleaved ADC based on a lookahead pipelined architecture using open-loop residue amplifiers in the pipeline, and a multi-channel equalizer coupled to the interleaved ADC, the multi-channel equalizer capable of applying different equalization to the different ADC channels.

8. The transceiver chip of claim 7 wherein the receive path circuitry further comprises:

a programmable gain amplifier that applies a variable gain to the 10 G electrical signal from the TIA port;

a multi-stage automatic gain control coupled between the interleaved ADC, the multi-channel equalizer and the programmable gain amplifier, for applying a variable gain to the programmable gain amplifier; and

a timing recovery circuit coupled to receive an output of the interleaved ADC and an error signal from the multi-channel equalizer, for driving a clock for the interleaved ADC.

9. The transceiver chip of claim 7 , wherein the multi-channel equalizer comprises:

a feedforward equalizer (FFE) coupled to a Viterbi decoder having a channel estimator.

10. The transceiver chip of claim 9 , wherein the FFE or the channel estimator for the Viterbi decoder is adapted on a sub-sampled basis using an LMS algorithm.

11. The transceiver chip of claim 7 , wherein the multi-channel equalizer applies an equalization that includes both a term based on shared coefficients for all ADC channels and another term based on channel-dependent coefficients.