Semiconductor integrated circuit
View Patent ↗In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value has been selected using a selection signal S 0 , a first node N 1 is L and a second node N 2 of a second dynamic circuit 1 B is H, so that an output signal Q has an H level. In this case, when none of a plurality of pieces of data D 0 to D 2 is selected using selection signals S 0 to S 2 , the first node N 1 is H, so that the electric charge of the second node N 2 is discharged and the output signal Q erroneously has an L level. However, in this case, an output node N 3 is H and a fourth node N 4 is L, so that an n-type transistor Tr 6 of the second dynamic circuit 1 B is turned OFF, thereby preventing the second node N 2 from being discharged. Therefore, a normal operation is performed while securing a satisfactorily high-speed operation even when none of the pieces of data is selected. This circuit is used in a predetermined circuit, such as, for example, a forwarding path of a data path, a crossbar bus switch, or an input portion of a reconfigurable processing unit.
1. A semiconductor integrated circuit, comprising:
a dynamic logic circuit receiving a plurality of data signals and a control signal, and outputting a first signal;
a static logic circuit receiving a data signal which is different from the plurality of data signals, and outputting a second signal; and
a holding circuit receiving the first signal and the second signal, and outputting a third signal,
wherein the first signal is received by the holding circuit without passing through the static logic circuit, and
the second signal is received by the holding circuit without passing through the dynamic logic circuit.
2. A semiconductor integrated circuit, wherein the semiconductor integrated circuit of claim 1 is a flip-flop circuit.
3. The semiconductor integrated circuit of claim 1 , wherein the control signal is a clock.
4. The semiconductor integrated circuit of claim 1 , wherein
the dynamic logic circuit comprises an internal signal line, and
the internal signal line is precharged or discharged by the control signal.
5. The semiconductor integrated circuit of claim 1 , wherein the data signal received by the static logic circuit is a scan signal.
6. The semiconductor integrated circuit of claim 1 , wherein the third signal has a data corresponding to one of an inversed data of the first signal and an inversed data of the second signal.
7. The semiconductor integrated circuit of claim 1 , wherein the static logic circuit is a scan input circuit.
8. A semiconductor integrated circuit, comprising:
a dynamic logic circuit having a plurality of first input lines for data signals and a first output line;
a static logic circuit having a second input line for a data signal and a second output line; and
a holding circuit having a first transistor, a second transistor, and a third output line,
wherein the first output line is coupled to a gate of the first transistor of the holding circuit, and
the second output line is coupled to a gate of the second transistor of the holding circuit.
9. A semiconductor integrated circuit, comprising:
a dynamic logic circuit having a plurality of first input terminals for data signal and a first output terminal;
a static logic circuit having a second input terminal for a data signal and a second output terminal; and
a holding circuit having a first transistor, a second transistor and a third output line,
wherein an output from the first output terminal of the dynamic logic circuit is input to a gate of the first transistor of the holding circuit, and
the second output from the second output terminal of the static logic circuit is input to a gate of the second transistor of the holding circuit.