Thin film transistor

1. A thin film transistor, comprising:

a substrate;

a patterned semiconductor layer disposed on the substrate and including at least two channel regions, a single source region and a single drain region; and

a gate electrode insulated from the semiconductor layer,

wherein the patterned semiconductor layer of the thin film transistor is disposed entirely within a single grain of silicon that was crystallized radially outwards from only a single point such that the single grain of silicon is surrounded by polycrystalline silicon, and wherein the patterned semiconductor layer partially surrounds an area where the single point had been.

2. The thin film transistor according to claim 1 , wherein the semiconductor layer is formed of silicon crystallized by a super grain silicon (SGS) crystallization method.

3. The thin film transistor according to claim 2 , wherein the SGS crystallization method includes forming an amorphous silicon layer, a capping layer and a metal catalyst layer on the substrate to provide a resulting structure that is the formed amorphous silicon layer, the capping layer and the metal catalyst layer on the substrate, and crystallizing the amorphous silicon layer into a polycrystalline silicon layer by heat-treating the resultant structure.

4. The thin film transistor according to claim 3 , wherein the capping layer is formed of a silicon nitride layer.

5. The thin film transistor according to claim 3 , wherein the metal catalyst layer is formed of at least one of Ni, Pd, Ti, Ag, Au, Al, Sn, Sb, Cu, Co, Mo, Cr, Ru, Rh, Cd and Pt.

6. The thin film transistor according to claim 1 , wherein the single point is a seed created by an SGS crystallization method.

7. A thin film transistor, comprising:

a substrate;

a patterned semiconductor layer disposed on the substrate and including at least two channel regions, a single source region and a single drain region; and

a gate electrode insulated from the semiconductor layer,

wherein the patterned semiconductor layer of the thin film transistor is located entirely within a single grain of silicon, wherein the single grain of silicon is surrounded by polycrystalline silicon, and wherein the patterned semiconductor layer includes a u-shaped portion that is open on one side.

8. The thin film transistor of claim 7 , wherein the u-shaped portion partially surrounds a central area of the single grain of silicon from which the patterned semiconductor layer was formed.

9. An intermediate structure in the fabrication of a thin film transistor, comprising:

a substrate;

a polycrystalline silicon layer having one or more grains, each grain having a single seed created by an SGS crystallization method, wherein the single seed is centrally located in the grain, and wherein the polycrystalline silicon layer has grain boundaries between adjacent grains; and

a mask layer disposed on the polycrystalline silicon layer, wherein the mask layer defines a pattern in the polycrystalline silicon layer for a semiconductor layer having two channels, wherein the mask layer is formed entirely within one grain of the polycrystalline silicon layer and wherein the mask layer partially surrounds the single seed.